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Date:      Mon, 14 Oct 2013 23:58:52 +0000 (UTC)
From:      Adrian Chadd <adrian@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org
Subject:   svn commit: r256483 - head/sys/mips/atheros
Message-ID:  <201310142358.r9ENwqYB046599@svn.freebsd.org>

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Author: adrian
Date: Mon Oct 14 23:58:52 2013
New Revision: 256483
URL: http://svnweb.freebsd.org/changeset/base/256483

Log:
  Add the rest of the AR934x SoC reset register definitions.
  
  Obtained from:	Linux/OpenWRT

Modified:
  head/sys/mips/atheros/ar934xreg.h

Modified: head/sys/mips/atheros/ar934xreg.h
==============================================================================
--- head/sys/mips/atheros/ar934xreg.h	Mon Oct 14 23:57:12 2013	(r256482)
+++ head/sys/mips/atheros/ar934xreg.h	Mon Oct 14 23:58:52 2013	(r256483)
@@ -103,16 +103,38 @@
 #define	AR934X_RESET_REG_BOOTSTRAP		(AR71XX_RST_BLOCK_BASE + 0xb0)
 #define	AR934X_RESET_REG_PCIE_WMAC_INT_STATUS	(AR71XX_RST_BLOCK_BASE + 0xac)
 
+#define	AR934X_RESET_HOST		(1 << 31)
+#define	AR934X_RESET_SLIC		(1 << 30)
+#define	AR934X_RESET_HDMA		(1 << 29)
+#define	AR934X_RESET_EXTERNAL		(1 << 28)
+#define	AR934X_RESET_RTC		(1 << 27)
+#define	AR934X_RESET_PCIE_EP_INT	(1 << 26)
+#define	AR934X_RESET_CHKSUM_ACC		(1 << 25)
+#define	AR934X_RESET_FULL_CHIP		(1 << 24)
 #define	AR934X_RESET_GE1_MDIO		(1 << 23)
 #define	AR934X_RESET_GE0_MDIO		(1 << 22)
+#define	AR934X_RESET_CPU_NMI		(1 << 21)
+#define	AR934X_RESET_CPU_COLD		(1 << 20)
+#define	AR934X_RESET_HOST_RESET_INT	(1 << 19)
+#define	AR934X_RESET_PCIE_EP		(1 << 18)
+#define	AR934X_RESET_UART1		(1 << 17)
+#define	AR934X_RESET_DDR		(1 << 16)
+#define	AR934X_RESET_USB_PHY_PLL_PWD_EXT	(1 << 15)
+#define	AR934X_RESET_NANDF		(1 << 14)
 #define	AR934X_RESET_GE1_MAC		(1 << 13)
 #define	AR934X_RESET_ETH_SWITCH_ANALOG	(1 << 12)
 #define	AR934X_RESET_USB_PHY_ANALOG	(1 << 11)
+#define	AR934X_RESET_HOST_DMA_INT	(1 << 10)
 #define	AR934X_RESET_GE0_MAC		(1 << 9)
 #define	AR934X_RESET_ETH_SWITCH		(1 << 8)
+#define	AR934X_RESET_PCIE_PHY		(1 << 7)
+#define	AR934X_RESET_PCIE		(1 << 6)
 #define	AR934X_RESET_USB_HOST		(1 << 5)
 #define	AR934X_RESET_USB_PHY		(1 << 4)
 #define	AR934X_RESET_USBSUS_OVERRIDE	(1 << 3)
+#define	AR934X_RESET_LUT		(1 << 2)
+#define	AR934X_RESET_MBOX		(1 << 1)
+#define	AR934X_RESET_I2S		(1 << 0)
 
 #define	AR934X_BOOTSTRAP_SW_OPTION8	(1 << 23)
 #define	AR934X_BOOTSTRAP_SW_OPTION7	(1 << 22)



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