Date: Fri, 29 Apr 2011 11:44:05 +0800 From: Adrian Chadd <adrian@freebsd.org> To: freebsd-mips@freebsd.org Subject: [AR71xx] Patch to flush DDR FIFO for IP2 interrupts Message-ID: <BANLkTinaL-f1FPeMXA%2BSVAeDvSTJ2GoBog@mail.gmail.com>
next in thread | raw e-mail | index | archive | help
[-- Attachment #1 --]
The Linux ar71xx/ar724x/ar913x interrupt handler flushes the DDR FIFO
before calling the IP2 interrupt handler. This patch introduces that
functionality to FreeBSD.
I'd appreciate a quick review; especially to ensure I'm actually
calling it for the right IRQ value. :-)
Thanks,
Adrian
[-- Attachment #2 --]
Index: apb.c
===================================================================
--- apb.c (revision 220911)
+++ apb.c (working copy)
@@ -42,6 +42,7 @@
#include <mips/atheros/apbvar.h>
#include <mips/atheros/ar71xxreg.h>
+#include <mips/atheros/ar71xx_cpudef.h>
#undef APB_DEBUG
#ifdef APB_DEBUG
@@ -345,6 +346,10 @@
continue;
}
+ /* Flush DDR FIFO for IP2 */
+ if (irq == 0)
+ ar71xx_device_ddr_flush_ip2();
+
/* TODO: frame instead of NULL? */
intr_event_handle(event, NULL);
mips_intrcnt_inc(sc->sc_intr_counter[irq]);
Index: ar71xx_cpudef.h
===================================================================
--- ar71xx_cpudef.h (revision 220911)
+++ ar71xx_cpudef.h (working copy)
@@ -51,7 +51,7 @@
* This flush is done before the IRQ is handled to make
* sure the driver correctly sees any memory updates.
*/
- void (* ar71xx_chip_irq_flush_ip2) (void);
+ void (* ar71xx_chip_ddr_flush_ip2) (void);
/*
* The USB peripheral init code is subtly different for
* each chip.
@@ -106,6 +106,11 @@
ar71xx_cpu_ops->ar71xx_chip_init_usb_peripheral();
}
+static inline void ar71xx_device_ddr_flush_ip2(void)
+{
+ ar71xx_cpu_ops->ar71xx_chip_ddr_flush_ip2();
+}
+
/* XXX shouldn't be here! */
extern uint32_t u_ar71xx_cpu_freq;
extern uint32_t u_ar71xx_ahb_freq;
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?BANLkTinaL-f1FPeMXA%2BSVAeDvSTJ2GoBog>