Date: Fri, 12 May 2006 03:55:05 -0000 From: "alpha_eda" <alpha_eda@yahoo.co.in> To: freebsd-scsi@freebsd.org Subject: Off Topic: Verification Engineers - World leader in EDA & Verification Solutions Message-ID: <e410up%2Burvo@eGroups.com>
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Hi, We have an excellent opportunity for Functional Verification Engineers to design and implement Verification IP, work closely with customers and partners. To be a part of this high-tech company you need to have 1) Solid experience to create test plans for functional and timing verification of the memory controller design IP coded in Verilog 2) Exposure to synthesis and STA reports and analysis 3) Debug expertise in tool flow for Verilog based designs and netlists 4) Understanding of simulation, synthesis and static timing products and their interfaces. Education: BE/B.Tech, M.E/M.Tech/MS in EE or CS Experience: 5 - 8 Years If your skills match the above requirements, we would like to talk to you. Send in your resume to paul@alphaeus.com or give a call on the number below Thanks Vinay Paul alphaeus HR Ph: +91-0-98807 74263(M) E-mail: paul@alphaeus.com
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