Date: Mon, 2 Sep 2013 21:46:35 GMT From: Robert Watson <rwatson@FreeBSD.org> To: Perforce Change Reviews <perforce@FreeBSD.org> Subject: PERFORCE change 558543 for review Message-ID: <201309022146.r82LkZGg095794@skunkworks.freebsd.org>
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http://p4web.freebsd.org/@@558543?ac=10 Change 558543 by rwatson@rwatson_zenith_cl_cam_ac_uk on 2013/09/02 21:45:38 Provide a stub (nop) implementation of CCall/CReturn via an installed software exception handler. Contents to be fleshed out over the coming days. Affected files ... .. //depot/projects/ctsrd/cheribsd/src/sys/mips/cheri/ccall.S#2 edit .. //depot/projects/ctsrd/cheribsd/src/sys/mips/include/cherireg.h#10 edit .. //depot/projects/ctsrd/cheribsd/src/sys/mips/mips/machdep.c#7 edit Differences ... ==== //depot/projects/ctsrd/cheribsd/src/sys/mips/cheri/ccall.S#2 (text+ko) ==== @@ -1,34 +1,68 @@ -#- -# Copyright (c) 2013 Robert N. M. Watson -# Copyright (c) 2013 Michael Roe -# All rights reserved. -# -# This software was developed by SRI International and the University of -# Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) -# ("CTSRD"), as part of the DARPA CRASH research programme. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# -# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND -# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE -# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -# SUCH DAMAGE. -# +/*- + * Copyright (c) 2013 Robert N. M. Watson + * Copyright (c) 2013 Michael Roe + * All rights reserved. + * + * This software was developed by SRI International and the University of + * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) + * ("CTSRD"), as part of the DARPA CRASH research programme. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* XXXRW: Can I drop some of these? */ +#include <machine/asm.h> +#include <machine/cpu.h> +#include <machine/regnum.h> +#include <machine/cpuregs.h> +#include <machine/pte.h> + +#ifdef CPU_CHERI +#include <machine/cheriasm.h> +#include <machine/cherireg.h> +#endif + +#include "assym.s" + +/* + * Software implementations of CCall, CReturn handlers for CHERI. + * + * XXXRW: Gubbins missing. + */ +VECTOR(CHERICCallVector, unknown) + .set push + .set noat +#ifdef CPU_CHERI + CHERI_EXCEPTION_ENTER(k0) +#endif + + /* XXXRW: For now, increment PC as though it were a no-op. */ + MFC0 k0, MIPS_COP_0_EXC_PC + PTR_ADDU k0, 4 + MTC0 k0, MIPS_COP_0_EXC_PC -# -# Software implementations of CCall, CReturn handlers for CHERI -# +#ifdef CPU_CHERI + CHERI_EXCEPTION_RETURN(k0) +#endif + eret + .set pop +VECTOR_END(CHERICCallVector) ==== //depot/projects/ctsrd/cheribsd/src/sys/mips/include/cherireg.h#10 (text+ko) ==== @@ -1,5 +1,5 @@ /*- - * Copyright (c) 2011-2012 Robert N. M. Watson + * Copyright (c) 2011-2013 Robert N. M. Watson * All rights reserved. * * This software was developed by SRI International and the University of @@ -218,4 +218,9 @@ #define CHERI_EXCCODE_ACCESS_KR1C 0x1d #define CHERI_EXCCODE_ACCESS_KR2C 0x1e +/* + * Location of the CHERI CCall/CReturn software-path exception vector. + */ +#define CHERI_CCALL_EXC_VEC ((intptr_t)(int32_t)0x80000280) + #endif /* _MIPS_INCLUDE_CHERIREG_H_ */ ==== //depot/projects/ctsrd/cheribsd/src/sys/mips/mips/machdep.c#7 (text+ko) ==== @@ -81,6 +81,9 @@ #include <machine/asm.h> #include <machine/bootinfo.h> #include <machine/cache.h> +#ifdef CPU_CHERI +#include <machine/cheri.h> +#endif #include <machine/clock.h> #include <machine/cpu.h> #include <machine/cpuregs.h> @@ -166,6 +169,9 @@ /* MIPS wait skip region */ extern char MipsWaitStart[], MipsWaitEnd[]; +/* CHERI CCall/CReturn software path */ +extern char CHERICCallVector[], CHERICCallVectorEnd[]; + extern char edata[], end[]; #ifdef DDB extern vm_offset_t ksym_start, ksym_end; @@ -363,6 +369,11 @@ bcopy(MipsCache, (void *)MIPS_CACHE_ERR_EXC_VEC, MipsCacheEnd - MipsCache); +#ifdef CPU_CHERI + bcopy(CHERICCallVector, (void *)CHERI_CCALL_EXC_VEC, + CHERICCallVectorEnd - CHERICCallVector); +#endif + /* * Clear out the I and D caches. */
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