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Date:      Thu, 21 Jun 2001 16:07:25 +0100
From:      David Malone <dwmalone@maths.tcd.ie>
To:        Andrew Gallatin <gallatin@cs.duke.edu>
Cc:        kaz@kobe1995.net, current@freebsd.org
Subject:   Re: support Pentium3 SSE
Message-ID:  <20010621160725.A76040@walton.maths.tcd.ie>
In-Reply-To: <15153.6187.437184.453161@grasshopper.cs.duke.edu>; from gallatin@cs.duke.edu on Wed, Jun 20, 2001 at 05:39:55PM -0400
References:  <20010620151416.A2601@walton.maths.tcd.ie> <200106201824.DAA10190@ns.kobe1995.net> <15153.6187.437184.453161@grasshopper.cs.duke.edu>

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On Wed, Jun 20, 2001 at 05:39:55PM -0400, Andrew Gallatin wrote:
> While we're at it, I know that the AMD AthlonMP supports SSE, but I
> can't seem to find which bits they're using in their features for it.
> It would be nice if somebody who knew that spoke up so that we
> supported SSE on Palamino right off the bat..

Is this page any good to you:

	http://www.sandpile.org/ia32/cpuid.htm

Otherwise, maybe we can ask someone in AMD.

	David.

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