Date: Sun, 27 Sep 2020 09:27:39 +0000 (UTC) From: Michal Meloun <mmel@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r366195 - head/sys/arm64/arm64 Message-ID: <202009270927.08R9RdaX063161@repo.freebsd.org>
next in thread | raw e-mail | index | archive | help
Author: mmel Date: Sun Sep 27 09:27:39 2020 New Revision: 366195 URL: https://svnweb.freebsd.org/changeset/base/366195 Log: Reapply r366193 with proper commit log. Don't map same physical memory multiple times with different cache attributes. This is explicitly stated as architectural undefined behavior, leading to coherency issues sooner or later. Modified: head/sys/arm64/arm64/locore.S Modified: head/sys/arm64/arm64/locore.S ============================================================================== --- head/sys/arm64/arm64/locore.S Sun Sep 27 09:24:31 2020 (r366194) +++ head/sys/arm64/arm64/locore.S Sun Sep 27 09:27:39 2020 (r366195) @@ -498,7 +498,7 @@ common: cbz x19, 1f /* Create the identity mapping for FDT data (2 MiB max) */ - mov x7, #(ATTR_S1_nG | ATTR_S1_IDX(VM_MEMATTR_UNCACHEABLE)) + mov x7, #(ATTR_S1_nG | ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK)) mov x9, x0 mov x8, x0 /* VA start (== PA start) */ mov x10, #1 @@ -508,7 +508,7 @@ common: #endif /* Create the VA = PA map */ - mov x7, #(ATTR_S1_nG | ATTR_S1_IDX(VM_MEMATTR_UNCACHEABLE)) + mov x7, #(ATTR_S1_nG | ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK)) mov x9, x27 mov x8, x9 /* VA start (== PA start) */ mov x10, #1
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?202009270927.08R9RdaX063161>