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Date:      Wed, 16 Dec 2020 08:03:07 +0000 (UTC)
From:      Vladimir Kondratyev <wulf@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-12@freebsd.org
Subject:   svn commit: r368690 - stable/12/sys/dev/ichiic
Message-ID:  <202012160803.0BG837MR034707@repo.freebsd.org>

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Author: wulf
Date: Wed Dec 16 08:03:07 2020
New Revision: 368690
URL: https://svnweb.freebsd.org/changeset/base/368690

Log:
  MFC r368366
  
  ig4(4): Add PCI IDs for Intel Tiger Lake
  
  Submitted by:	Neel Chauhan <neel AT neelc DOT org>
  Differential Revision:	https://reviews.freebsd.org/D27483

Modified:
  stable/12/sys/dev/ichiic/ig4_iic.c
  stable/12/sys/dev/ichiic/ig4_pci.c
  stable/12/sys/dev/ichiic/ig4_var.h
Directory Properties:
  stable/12/   (props changed)

Modified: stable/12/sys/dev/ichiic/ig4_iic.c
==============================================================================
--- stable/12/sys/dev/ichiic/ig4_iic.c	Wed Dec 16 07:59:47 2020	(r368689)
+++ stable/12/sys/dev/ichiic/ig4_iic.c	Wed Dec 16 08:03:07 2020	(r368690)
@@ -119,6 +119,12 @@ static const struct ig4_hw ig4iic_hw[] = {
 		.ic_clock_rate = 216,
 		.sda_hold_time = 230,
 	},
+	[IG4_TIGERLAKE] = {
+		.ic_clock_rate = 133,
+		.sda_fall_time = 171,
+		.scl_fall_time = 208,
+		.sda_hold_time = 42,
+	},
 };
 
 static int ig4iic_set_config(ig4iic_softc_t *sc, bool reset);

Modified: stable/12/sys/dev/ichiic/ig4_pci.c
==============================================================================
--- stable/12/sys/dev/ichiic/ig4_pci.c	Wed Dec 16 07:59:47 2020	(r368689)
+++ stable/12/sys/dev/ichiic/ig4_pci.c	Wed Dec 16 08:03:07 2020	(r368690)
@@ -121,6 +121,21 @@ static int ig4iic_pci_detach(device_t dev);
 #define PCI_CHIP_COMETLAKE_V_I2C_1	0xa3e18086
 #define PCI_CHIP_COMETLAKE_V_I2C_2	0xa3e28086
 #define PCI_CHIP_COMETLAKE_V_I2C_3	0xa3e38086
+#define PCI_CHIP_TIGERLAKE_H_I2C_0	0x43d88086
+#define PCI_CHIP_TIGERLAKE_H_I2C_1	0x43e88086
+#define PCI_CHIP_TIGERLAKE_H_I2C_2	0x43e98086
+#define PCI_CHIP_TIGERLAKE_H_I2C_3	0x43ea8086
+#define PCI_CHIP_TIGERLAKE_H_I2C_4	0x43eb8086
+#define PCI_CHIP_TIGERLAKE_H_I2C_5	0x43ad8086
+#define PCI_CHIP_TIGERLAKE_H_I2C_6	0x43ae8086
+#define PCI_CHIP_TIGERLAKE_LP_I2C_0	0xa0c58086
+#define PCI_CHIP_TIGERLAKE_LP_I2C_1	0xa0c68086
+#define PCI_CHIP_TIGERLAKE_LP_I2C_2	0xa0d88086
+#define PCI_CHIP_TIGERLAKE_LP_I2C_3	0xa0d98086
+#define PCI_CHIP_TIGERLAKE_LP_I2C_4	0xa0e88086
+#define PCI_CHIP_TIGERLAKE_LP_I2C_5	0xa0e98086
+#define PCI_CHIP_TIGERLAKE_LP_I2C_6	0xa0ea8086
+#define PCI_CHIP_TIGERLAKE_LP_I2C_7	0xa0eb8086
 
 struct ig4iic_pci_device {
 	uint32_t	devid;
@@ -184,6 +199,21 @@ static struct ig4iic_pci_device ig4iic_pci_devices[] =
 	{ PCI_CHIP_COMETLAKE_V_I2C_1, "Intel Comet Lake-V I2C Controller-1", IG4_CANNONLAKE},
 	{ PCI_CHIP_COMETLAKE_V_I2C_2, "Intel Comet Lake-V I2C Controller-2", IG4_CANNONLAKE},
 	{ PCI_CHIP_COMETLAKE_V_I2C_3, "Intel Comet Lake-V I2C Controller-3", IG4_CANNONLAKE},
+	{ PCI_CHIP_TIGERLAKE_H_I2C_0, "Intel Tiger Lake-H I2C Controller-0", IG4_TIGERLAKE},
+	{ PCI_CHIP_TIGERLAKE_H_I2C_1, "Intel Tiger Lake-H I2C Controller-1", IG4_TIGERLAKE},
+	{ PCI_CHIP_TIGERLAKE_H_I2C_2, "Intel Tiger Lake-H I2C Controller-2", IG4_TIGERLAKE},
+	{ PCI_CHIP_TIGERLAKE_H_I2C_3, "Intel Tiger Lake-H I2C Controller-3", IG4_TIGERLAKE},
+	{ PCI_CHIP_TIGERLAKE_H_I2C_4, "Intel Tiger Lake-H I2C Controller-4", IG4_TIGERLAKE},
+	{ PCI_CHIP_TIGERLAKE_H_I2C_5, "Intel Tiger Lake-H I2C Controller-5", IG4_TIGERLAKE},
+	{ PCI_CHIP_TIGERLAKE_H_I2C_6, "Intel Tiger Lake-H I2C Controller-6", IG4_TIGERLAKE},
+	{ PCI_CHIP_TIGERLAKE_LP_I2C_0, "Intel Tiger Lake-LP I2C Controller-0", IG4_SKYLAKE},
+	{ PCI_CHIP_TIGERLAKE_LP_I2C_1, "Intel Tiger Lake-LP I2C Controller-1", IG4_SKYLAKE},
+	{ PCI_CHIP_TIGERLAKE_LP_I2C_2, "Intel Tiger Lake-LP I2C Controller-2", IG4_SKYLAKE},
+	{ PCI_CHIP_TIGERLAKE_LP_I2C_3, "Intel Tiger Lake-LP I2C Controller-3", IG4_SKYLAKE},
+	{ PCI_CHIP_TIGERLAKE_LP_I2C_4, "Intel Tiger Lake-LP I2C Controller-4", IG4_SKYLAKE},
+	{ PCI_CHIP_TIGERLAKE_LP_I2C_5, "Intel Tiger Lake-LP I2C Controller-5", IG4_SKYLAKE},
+	{ PCI_CHIP_TIGERLAKE_LP_I2C_6, "Intel Tiger Lake-LP I2C Controller-6", IG4_SKYLAKE},
+	{ PCI_CHIP_TIGERLAKE_LP_I2C_7, "Intel Tiger Lake-LP I2C Controller-7", IG4_SKYLAKE},
 };
 
 static int

Modified: stable/12/sys/dev/ichiic/ig4_var.h
==============================================================================
--- stable/12/sys/dev/ichiic/ig4_var.h	Wed Dec 16 07:59:47 2020	(r368689)
+++ stable/12/sys/dev/ichiic/ig4_var.h	Wed Dec 16 08:03:07 2020	(r368690)
@@ -43,10 +43,17 @@
 #include "pci_if.h"
 #include "iicbus_if.h"
 
-enum ig4_vers { IG4_HASWELL, IG4_ATOM, IG4_SKYLAKE, IG4_APL, IG4_CANNONLAKE };
+enum ig4_vers {
+	IG4_HASWELL,
+	IG4_ATOM,
+	IG4_SKYLAKE,
+	IG4_APL,
+	IG4_CANNONLAKE,
+	IG4_TIGERLAKE
+};
+
 /* Controller has additional registers */
-#define	IG4_HAS_ADDREGS(vers)	((vers) == IG4_SKYLAKE || \
-	(vers) == IG4_APL || (vers) == IG4_CANNONLAKE)
+#define	IG4_HAS_ADDREGS(vers)	((vers) >= IG4_SKYLAKE)
 
 struct ig4_hw {
 	uint32_t	ic_clock_rate;	/* MHz */



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