Date: Tue, 18 Oct 2005 07:40:58 -0700 From: "David O'Brien" <obrien@FreeBSD.org> To: Andrew Gallatin <gallatin@cs.duke.edu> Cc: cvs-src@FreeBSD.org, src-committers@FreeBSD.org, David Xu <davidxu@FreeBSD.org>, cvs-all@FreeBSD.org Subject: Re: cvs commit: src/sys/amd64/amd64 cpu_switch.S machdep.c Message-ID: <20051018144058.GA84920@dragon.NUXI.org> In-Reply-To: <20051018094402.A29138@grasshopper.cs.duke.edu> References: <200510172310.j9HNAVPL013057@repoman.freebsd.org> <20051018094402.A29138@grasshopper.cs.duke.edu>
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On Tue, Oct 18, 2005 at 09:44:02AM -0400, Andrew Gallatin wrote: > It is a shame we can't find a way to use the TSC as a timecounter on > SMP systems. It seems that about 40% of the context switch time is > spent just waiting for the PIO read of the ACPI-fast or i8254 to > return. Revision F Opterion's will have the RDTSCP (read serialized TSC pair) instruction that helps some. Slide 13 of http://www.amd.com/us-en/assets/content_type/DownloadableAssets/dwamd_kernel_summit_08_RB.pdf Future Opteron's (or what ever AMD will call it then) will have a P-state invarient TSC in 2007. http://lwn.net/Articles/144098/ -- -- David (obrien@FreeBSD.org)
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