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Date:      Tue, 13 Feb 2001 03:02:19 -0800 (PST)
From:      Ying-Chieh Liao <ijliao@FreeBSD.org>
To:        cvs-committers@FreeBSD.org, cvs-all@FreeBSD.org
Subject:   cvs commit: ports/cad Makefile ports/cad/iverilog Makefile distinfo pkg-comment pkg-descr pkg-plist
Message-ID:  <200102131102.f1DB2K975999@freefall.freebsd.org>
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ijliao      2001/02/13 03:02:19 PST

  Modified files:
    cad                  Makefile 
  Added files:
    cad/iverilog         Makefile distinfo pkg-comment pkg-descr 
                         pkg-plist 
  Log:
  add iverilog, a Verilog simulation and synthesis tool
  
  Revision  Changes    Path
  1.20      +2 -1      ports/cad/Makefile



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