Date: Sun, 23 Mar 1997 04:03:18 +0900 From: KATO Takenori <kato@eclogite.eps.nagoya-u.ac.jp> To: current@freebsd.org Subject: New CPU identification and initializatino routine Message-ID: <199703221903.EAA00372@gneiss.eps.nagoya-u.ac.jp>
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I have just commited new CPU identification routines. Main features
of this change are as follows:
A. Automatic CPU identification
1. Identify all Cyrix CPUs including M2.
2. Identify IBM Blue Lightning CPU.
3. Identify AMD Nx586 CPU.
B. CPU initialization
1. Initialize special registers of Cyrix CPU.
2. Initialize msr of IBM Blue Lightning CPU.
3. Cyrix 6x86 CPU cache is enabled in write-through mode if revision
of CPU < 2.7. This feature can be disabled by kernel
configuration option.
Kernel configuration time options are as follows:
---------- BEGIN ----------
# Options for CPU features.
#
# CPU_BLUELIGHTNING_FPU_OP_CACHE enables FPU operand cache on IBM
# BlueLightning CPU. It works only with Cyrix FPU, and this option
# should not be used with Intel FPU.
#
# CPU_BLUELIGHTNING_3X enables triple-clock mode on IBM Blue Lightning
# CPU if CPU supports it. The default is double-clock mode on
# BlueLightning CPU box.
#
# CPU_BTB_EN enables branch target buffer on Cyrix 5x86 (NOTE 1).
#
# CPU_DISABLE_5X86_LSSER disables load store serialize (i.e. enables
# reorder). This option should not be used if you use memory mapped
# I/O device(s).
#
# CPU_FASTER_5X86_FPU enables faster FPU exception handler.
#
# CPU_I486_ON_386 enables CPU cache on i486 based CPU upgrade products
# for i386 machines.
# CPU_IORT defines I/O clock delay time (NOTE 1). Default vaules of
# I/O clock delay time on Cyrix 5x86 and 6x86 are 0 and 7,respectively
# (no clock delay).
#
# CPU_LOOP_EN prevents flushing the prefetch buffer if the destination
# of a jump is already present in the prefetch buffer on Cyrix 5x86(NOTE
# 1).
#
# CPU_RSTK_EN enables return stack on Cyrix 5x86 (NOTE 1).
#
# CPU_SUSP_HLT enables suspend on HALT. If this option is set, CPU
# enters suspend mode following execution of HALT instruction.
#
# CYRIX_CACHE_WORKS enables CPU cache on Cyrix 486 CPUs with cache
# flush at hold state.
#
# CYRIX_CACHE_REALLY_WORKS enables (1) CPU cache on Cyrix 486 CPUs
# without cache flush at hold state, and (2) write-back CPU cache on
# Cyrix 6x86 whose revision < 2.7 (NOTE 2).
#
# NOTE 1: The options, CPU_BTB_EN, CPU_LOOP_EN, CPU_IORT,
# CPU_LOOP_ENand CPU_RSTK_EN should no be used becasue of CPU bugs.
# These options may crash your system.
#
# NOTE 2: If CYRIX_CACHE_REALLY_WORKS is not set, CPU cache is enabled
# in write-through mode when revision < 2.7. If revision of Cyrix
# 6x86 >= 2.7, CPU cache is always enabled in write-back mode.
#
options CPU_BLUELIGHTNING_FPU_OP_CACHE
options "CPU_BLUELIGHTNING_3X"
options CPU_BTB_EN
options "CPU_DISABLE_5X86_LSSER"
options "CPU_FASTER_5X86_FPU"
options "CPU_I486_ON_386"
options CPU_IORT
options CPU_LOOP_EN
options CPU_RSTK_EN
options CPU_SUSP_HLT
options CYRIX_CACHE_WORKS
options CYRIX_CACHE_REALLY_WORKS
---------- END ---------
If you find any problem, please let me know.
Enjoy!
----
KATO Takenori <kato@eclogite.eps.nagoya-u.ac.jp>
Dept. Earth Planet. Sci., Nagoya Univ., Nagoya, 464-01, Japan
PGP public key: finger kato@eclogite.eps.nagoya-u.ac.jp
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