Date: Thu, 10 Apr 2008 19:26:09 -0400 From: Jung-uk Kim <jkim@FreeBSD.org> To: freebsd-current@FreeBSD.org Cc: Gary Stanley <gary@velocity-servers.net>, Poul-Henning Kamp <phk@phk.freebsd.dk> Subject: Re: TSC Timecounter and multi-core/SMP Message-ID: <200804101926.11343.jkim@FreeBSD.org> In-Reply-To: <20080410223849.17C278FC24@mx1.freebsd.org> References: <Your message of "Thu, 10 Apr 2008 13:52:28 MST." <47FE7E0C.4070801@FreeBSD.org> <1248.1207863941@critter.freebsd.dk> <20080410223849.17C278FC24@mx1.freebsd.org>
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On Thursday 10 April 2008 06:21 pm, Gary Stanley wrote: > At 05:45 PM 4/10/2008, Poul-Henning Kamp wrote: > >In message <47FE7E0C.4070801@FreeBSD.org>, Maxim Sobolev writes: > > >Kris Kennaway wrote: > > >> gnn@freebsd.org wrote: > > >>> Howdy, > > >>> > > >>> Is the TSC timecounter synchronized across multiple cores > > >>> and/or processors? A quick search seems to indicate it's not > > >>> but I'd like to find a definitive reference on the TSC. > > >> > > >> Modern Intel systems tend to be synchronized, in my > > >> experience. > > > > > >I really doubt they are. As far as I know newest milti-core > > > chips can modulate frequency of even suspend individual cores > > > independently of each other, which would make such > > > synchronization difficult to maintain if the power management > > > is on. > > > >P4 (and I think most newer chips) have a TSC that runs independent > >of the cpu clock frequency, and supposedly, always at constant > > rate. > > Are you talking about the RDTSCP? I think its only on newer > opterons and phenoms. I think you got it confused with "TscInvariant" feature: http://ltt.polymtl.ca/svn/ltt/branches/poly/doc/developer/tsc.txt "Because using the TSC for fast timer APIs is a desirable feature that helps performance, AMD has defined a CPUID feature bit that software can test to determine if the TSC is invariant. Issuing a CPUID instruction with an %eax register value of 0x8000_0007, on a processor whose base family is 0xF, returns "Advanced Power Management Information" in the %eax, %ebx, %ecx, and %edx registers. Bit 8 of the return %edx is the "TscInvariant" feature flag which is set when TSC is P-state, C-state, and STPCLK-throttling invariant; it is clear otherwise." RDTSCP is not P-state invariant. RDTSCP returns CPU ID with it, nothing more. Even if you have TscInvariant CPUs, I am not sure TSCs between cores/packages are synchronized. Jung-uk Kim
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