Date: Sun, 2 May 2004 21:20:45 +1000 (EST) From: Bruce Evans <bde@zeta.org.au> To: Mike Silbersack <silby@silby.com> Cc: cvs-all@freebsd.org Subject: Re: cvs commit: src/sys/i386/isa clock.c Message-ID: <20040502211748.X649@gamplex.bde.org> In-Reply-To: <20040501184603.I1080@odysseus.silby.com> References: <200404272003.i3RK3RFZ048001@repoman.freebsd.org> <20040430221434.J749@odysseus.silby.com> <20040501044209.L704@odysseus.silby.com> <20040501184603.I1080@odysseus.silby.com>
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On Sat, 1 May 2004, Mike Silbersack wrote: > On Sat, 1 May 2004, Bruce Evans wrote: > > HZ=1000 instead of the default of HZ=10 increases the chance of the > > timer wrapping while DELAY() is interrupted. This shouldn't be a > > problem for TSC calibration. > > Apparently it is a problem, somehow. :) I checked that CPU interruptes are disabled here. They still are. So the calibration can't be interrupted by a maskable interrupt. Bruce
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