Date: Fri, 20 Dec 2002 09:45:01 +0100 From: Thomas Nystrom <thn@saeab.se> To: Barry Pederson <bp@barryp.org> Cc: Steve Burton <steve@sliderule.demon.co.uk>, stable@FreeBSD.ORG Subject: Re: VIA VT6103 Ethernet Controller Question Message-ID: <3E02D88D.2A22FBD6@saeab.se> References: <3DFBACE7.1D60335F@saeab.se> <3E01DE5A.265553D0@sliderule.demon.co.uk> <3E026002.5CDDA536@sliderule.demon.co.uk> <3E028E50.9080602@barryp.org> <3E029339.1050601@barryp.org>
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This is a multi-part message in MIME format. --------------20A548C44F24CDBCB678D91E Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Barry Pederson wrote: > > Oops, guess the 6103 is just a tranceiver, the 6102 is the controller - the > two go together. > > http://www.via.com.tw/en/datasheet/DS6103110.pdf > > which explains why the old EPIA boards show up as VT6102 in dmesg, even > though the website and manual only mentions VT6103. I think I'll shut up > now (but I'd still guess the EPIA-M networking is the same as the plain EPIA) Yeah, but it seems that there are some obscure differences between the integrated 6102 and the standalone 6102. Some reports saying that the integrated one can't connect to the 6103 (the PHY). I have looked at VIA's drivers and they are settning one bit to turn on the MII-interface (to the PHY). The attached patch does this, someone wants to try...? Please report the result (including an output of a 'pciconf -lv')! /thn -- --------------------------------------------------------------- Svensk Aktuell Elektronik AB Thomas Nyström Box 10 Phone: +46 8 35 92 85 S-191 21 Sollentuna Fax: +46 8 59 47 45 36 Sweden Email: thn@saeab.se --------------------------------------------------------------- --------------20A548C44F24CDBCB678D91E Content-Type: text/plain; charset=us-ascii; name="vr.patch.miion" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="vr.patch.miion" diff -u org/if_vr.c ./if_vr.c --- org/if_vr.c Thu Dec 19 19:51:51 2002 +++ ./if_vr.c Thu Dec 19 19:53:52 2002 @@ -739,6 +739,9 @@ /* Reset the adapter. */ vr_reset(sc); + /* Turn on bit2 (MIION) in PCI configuration register 0x53 during initialization */ + pci_write_config(dev, VR_PCI_MODE, pci_read_config(dev, VR_PCI_MODE, 4)|(VR_MODE3_MIION<<24), 4); + /* * Get station address. The way the Rhine chips work, * you're not allowed to directly access the EEPROM once diff -u org/if_vrreg.h ./if_vrreg.h --- org/if_vrreg.h Thu Dec 19 19:52:43 2002 +++ ./if_vrreg.h Thu Dec 19 19:53:47 2002 @@ -540,6 +540,9 @@ #define VR_PCI_MINLAT 0x0F #define VR_PCI_RESETOPT 0x48 #define VR_PCI_EEPROM_DATA 0x4C +#define VR_PCI_MODE 0x50 + +#define VR_MODE3_MIION 0x04 /* power management registers */ #define VR_PCI_CAPID 0xDC /* 8 bits */ --------------20A548C44F24CDBCB678D91E-- To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-stable" in the body of the message
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