Date: Tue, 12 Apr 2005 10:40:10 -0400 From: "Don Bowman" <don@SANDVINE.com> To: "Marc Olzheim" <marcolz@stack.nl>, "Aaron Summers" <aaronsummers@gmail.com>, <carlos@infodrive.com.ar> Cc: stable@freebsd.org Subject: RE: SuperMicro X5DP8-G2MB/(2)XEON 2.4/1GB RAM 5.4-S Freeze Message-ID: <2BCEB9A37A4D354AA276774EE13FB8C23A6B41@mailserver.sandvine.com>
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[-- Attachment #1 --]
From: Marc Olzheim
> On Mon, Apr 11, 2005 at 10:12:32PM -0400, Aaron Summers wrote:
> > We have a SuperMicro X5DP8-G2 Motherboard, 2xXEON 2.4, 1GB
> RAM server
> > running 5.4-STABLE that keeps freezing up. We have
> replaced RAM, HD,
> > SCSI controller, etc. To no avail. We are running SMP GENERIC
> > Kernel. I cannot get the system to panic, leave a core
> dump, etc. It
> > just always freezes. The server functions as a web server in a
> > HSphere Cluster. I am about out of options besides loading 4.11
> > (since our 4 series servers never die). Any help, feedback, clues,
> > similar experiences, etc would be greatly appreciated.
> >
> > On SCSI: The onboard Adaptec 7902 gives a dump on bootup
> but appears
> > to work. I read the archived post about this issue. The
> system still
> > locked up with an Adaptec 7982B that did not give this message.
>
The problem is with the periodic SMM interrupt and the bios.
The attached program (ich-periodic-smm-disable.c) will fix the problem.
For more information on what it does, see the Intel ICH3 datasheet.
compile as 'gcc ich-periodic-smm-disable.c; ./a.out' and you will be
good.
Run this on each boot.
I think you only need to clear PERIODIC_EN.
--don
[-- Attachment #2 --]
/*
* Copyright (C) 2005 Sandvine Incorporated. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <stdio.h>
#include <unistd.h>
#include <fcntl.h>
#include <sys/ioctl.h>
#include <sys/memrange.h>
#include <sys/pciio.h>
#include <sys/types.h>
#include <sys/mman.h>
#include <machine/cpufunc.h>
#define ICH_PMBASE 0x40 /* ACPI base address register */
#define INTEL_VENDORID 0x8086
#define INTEL_DEVICEID_ICH4 0x24c0
/* 82081CA (ICH3-S) LPC Interface bridge */
#define INTEL_DEVICEID_ICH3 0x2480
/* 82801EB/ER (ICH5) LPC Interface Bridge */
#define INTEL_DEVICEID_ICH5 0x24d0
int
clearPeriodicBits(u_int pmbase)
{
u_int smi_en;
smi_en = inl(pmbase + 0x30);
/* This disables SMI for the entire system.
* This may not be what you want for e.g. ACPI or APM
*/
smi_en = smi_en & (~((1<<14)| /* PERIODIC_EN */
(1<<13)| /* TCO_EN */
(1<<11)| /* MCSMI_EN */
(1<<6) | /* SWSMI_TMR_EN */
(1<<5) | /* APMC_EN */
(1<<4) | /* SLP_SMI_EN */
(1<<3) | /* LEGACY_USB_EN */
(1<<2) | /* BIOS_EN */
(1<<0))); /* GLBL_SMI_EN */
/* Disable the TCO counter to generate SMI */
outl(pmbase+0x30, smi_en);
}
int
clearPeriodic(int fd,
unsigned int vendorid,
unsigned int deviceid)
{
u_int pmbase;
struct pci_io io;
struct pci_conf_io pciio;
struct pci_match_conf mc;
struct pci_conf match;
memset(&pciio,0,sizeof(pciio));
memset(&mc, 0, sizeof(mc));
memset(&match, 0, sizeof(match));
mc.pc_vendor = vendorid; /* Intel */
mc.pc_device = deviceid; /* ICH3 LPC <-> PCI ISA bridge */
mc.flags = PCI_GETCONF_MATCH_VENDOR | PCI_GETCONF_MATCH_DEVICE;
pciio.patterns = &mc;
pciio.pat_buf_len = sizeof(mc);
pciio.num_patterns = 1;
pciio.matches = &match;
pciio.match_buf_len = sizeof(match);
if (ioctl(fd, PCIOCGETCONF, &pciio) < 0)
{
perror("PCIOCGETCONF");
return 1;
}
if (pciio.num_matches == 0)
{
return 1;
}
io.pi_sel = match.pc_sel;
io.pi_reg = ICH_PMBASE;
io.pi_width = 4;
if (ioctl(fd, PCIOCREAD, &io) < 0)
{
perror("PCIOCREAD");
return 1;
}
pmbase = ((u_int )io.pi_data) / 2 * 2;
printf("Found ICH device @ %u.%u.%u. pmbase = %08x\n",
match.pc_sel.pc_bus,
match.pc_sel.pc_dev,
match.pc_sel.pc_func, pmbase);
clearPeriodicBits(pmbase);
}
int
main(int argc, char **argv)
{
int fd1, fd2;
fd1 = open("/dev/pci", O_RDWR, 0);
if (fd1 < 0)
{
perror("open /dev/pci");
}
fd2 = open("/dev/io", O_RDWR, 0);
if (fd2 < 0)
{
perror("open /dev/io");
}
clearPeriodic(fd1, INTEL_VENDORID,INTEL_DEVICEID_ICH3);
}
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