Date: Tue, 4 Apr 2017 06:17:00 +0000 (UTC) From: David C Somayajulu <davidcs@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r316485 - in head: share/man/man4 sys/conf sys/dev/qlnx sys/dev/qlnx/qlnxe sys/modules sys/modules/qlnx sys/modules/qlnx/qlnxe Message-ID: <201704040617.v346H0Eg007675@repo.freebsd.org>
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Author: davidcs Date: Tue Apr 4 06:16:59 2017 New Revision: 316485 URL: https://svnweb.freebsd.org/changeset/base/316485 Log: Add 25/40/100Gigabit Ethernet Driver version v1.3.0 for Cavium Inc's. Qlogic 45000 Series Adapters MFC after:2 weeks Added: head/share/man/man4/qlnxe.4 (contents, props changed) head/sys/dev/qlnx/ head/sys/dev/qlnx/qlnxe/ head/sys/dev/qlnx/qlnxe/bcm_osal.h (contents, props changed) head/sys/dev/qlnx/qlnxe/common_hsi.h (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore.h (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_chain.h (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_cxt.c (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_cxt.h (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_cxt_api.h (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_dbg_fw_funcs.c (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_dbg_fw_funcs.h (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_dbg_values.h (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_dcbx.c (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_dcbx.h (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_dcbx_api.h (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_dev.c (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_dev_api.h (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_fcoe.h (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_fcoe_api.h (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_gtt_reg_addr.h (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_gtt_values.h (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_hsi_common.h (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_hsi_debug_tools.h (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_hsi_eth.h (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_hsi_fcoe.h (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_hsi_init_func.h (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_hsi_init_tool.h (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_hsi_iscsi.h (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_hsi_iwarp.h (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_hsi_rdma.h (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_hsi_roce.h (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_hw.c (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_hw.h (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_hw_defs.h (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.h (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_init_ops.c (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_init_ops.h (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_init_values.h (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_int.c (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_int.h (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_int_api.h (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_iov_api.h (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_iro.h (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_iro_values.h (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_iscsi.h (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_iscsi_api.h (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_l2.c (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_l2.h (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_l2_api.h (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_ll2.h (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_ll2_api.h (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_mcp.c (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_mcp.h (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_mcp_api.h (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_ooo.h (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_proto_if.h (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_roce.h (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_roce_api.h (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_rt_defs.h (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_sp_api.h (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_sp_commands.c (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_sp_commands.h (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_spq.c (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_spq.h (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_sriov.h (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_status.h (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_utils.h (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_vf.h (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_vf_api.h (contents, props changed) head/sys/dev/qlnx/qlnxe/ecore_vfpf_if.h (contents, props changed) head/sys/dev/qlnx/qlnxe/eth_common.h (contents, props changed) head/sys/dev/qlnx/qlnxe/fcoe_common.h (contents, props changed) head/sys/dev/qlnx/qlnxe/iscsi_common.h (contents, props changed) head/sys/dev/qlnx/qlnxe/iwarp_common.h (contents, props changed) head/sys/dev/qlnx/qlnxe/mcp_private.h (contents, props changed) head/sys/dev/qlnx/qlnxe/mcp_public.h (contents, props changed) head/sys/dev/qlnx/qlnxe/mfw_hsi.h (contents, props changed) head/sys/dev/qlnx/qlnxe/nvm_cfg.h (contents, props changed) head/sys/dev/qlnx/qlnxe/nvm_map.h (contents, props changed) head/sys/dev/qlnx/qlnxe/pcics_reg_driver.h (contents, props changed) head/sys/dev/qlnx/qlnxe/qlnx_def.h (contents, props changed) head/sys/dev/qlnx/qlnxe/qlnx_ioctl.c (contents, props changed) head/sys/dev/qlnx/qlnxe/qlnx_ioctl.h (contents, props changed) head/sys/dev/qlnx/qlnxe/qlnx_os.c (contents, props changed) head/sys/dev/qlnx/qlnxe/qlnx_os.h (contents, props changed) head/sys/dev/qlnx/qlnxe/qlnx_ver.h (contents, props changed) head/sys/dev/qlnx/qlnxe/rdma_common.h (contents, props changed) head/sys/dev/qlnx/qlnxe/reg_addr.h (contents, props changed) head/sys/dev/qlnx/qlnxe/roce_common.h (contents, props changed) head/sys/dev/qlnx/qlnxe/spad_layout.h (contents, props changed) head/sys/dev/qlnx/qlnxe/storage_common.h (contents, props changed) head/sys/dev/qlnx/qlnxe/tcp_common.h (contents, props changed) head/sys/modules/qlnx/ head/sys/modules/qlnx/Makefile (contents, props changed) head/sys/modules/qlnx/qlnxe/ head/sys/modules/qlnx/qlnxe/Makefile (contents, props changed) Modified: head/share/man/man4/Makefile head/sys/conf/files.amd64 head/sys/modules/Makefile Modified: head/share/man/man4/Makefile ============================================================================== --- head/share/man/man4/Makefile Tue Apr 4 05:56:42 2017 (r316484) +++ head/share/man/man4/Makefile Tue Apr 4 06:16:59 2017 (r316485) @@ -426,6 +426,7 @@ MAN= aac.4 \ ${_qlxge.4} \ ${_qlxgb.4} \ ${_qlxgbe.4} \ + ${_qlnxe.4} \ ral.4 \ random.4 \ rc.4 \ @@ -846,11 +847,13 @@ _ntb_transport.4=ntb_transport.4 _qlxge.4= qlxge.4 _qlxgb.4= qlxgb.4 _qlxgbe.4= qlxgbe.4 +_qlnxe.4= qlnxe.4 _sfxge.4= sfxge.4 MLINKS+=qlxge.4 if_qlxge.4 MLINKS+=qlxgb.4 if_qlxgb.4 MLINKS+=qlxgbe.4 if_qlxgbe.4 +MLINKS+=qlnxe.4 if_qlnxe.4 MLINKS+=sfxge.4 if_sfxge.4 .if ${MK_BHYVE} != "no" Added: head/share/man/man4/qlnxe.4 ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/share/man/man4/qlnxe.4 Tue Apr 4 06:16:59 2017 (r316485) @@ -0,0 +1,90 @@ +.\"- +.\" Copyright (c) 2017 Cavium Inc. +.\" All rights reserved. +.\" +.\" Redistribution and use in source and binary forms, with or without +.\" modification, are permitted provided that the following conditions +.\" are met: +.\" 1. Redistributions of source code must retain the above copyright +.\" notice, this list of conditions and the following disclaimer. +.\" 2. Redistributions in binary form must reproduce the above copyright +.\" notice, this list of conditions and the following disclaimer in the +.\" documentation and/or other materials provided with the distribution. +.\" +.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +.\" SUCH DAMAGE. +.\" +.\" $FreeBSD$ +.\" +.Dd March 24, 2017 +.Dt QLNXE 4 +.Os +.Sh NAME +.Nm qlnxe +.Nd "Cavium 25/40/100 Gigabit Ethernet & CNA Adapter Driver" +.Sh SYNOPSIS +To compile this driver into the kernel, +place the following lines in your +kernel configuration file: +.Bd -ragged -offset indent +.Cd "device qlnxe" +.Ed +.Pp +To load the driver as a +module at boot time, place the following line in +.Xr loader.conf 5 : +.Bd -literal -offset indent +if_qlnxe_load="YES" +.Ed +.Sh DESCRIPTION +The +.Nm +driver supports IPv4 checksum offload, +TCP and UDP checksum offload for both IPv4 and IPv6, +Large Segment Offload for both IPv4 and IPv6, +Jumbo frames, VLAN Tag, Receive Side scaling, HW and Soft LRO. +For further hardware information, see +.Pa http://www.qlogic.com/ . +.Sh HARDWARE +The +.Nm +driver supports 25/40/100 Gigabit Ethernet & CNA Adapter based on the following +chipsets: +.Pp +.Bl -bullet -compact +.It +QLogic 45000 series +.El +.Sh SUPPORT +For support questions please contact your Cavium approved reseller or +Cavium Technical Support at +.Pa http://support.qlogic.com , +or by E-mail at +.Aq Mt support@qlogic.com . +.Sh SEE ALSO +.Xr altq 4 , +.Xr arp 4 , +.Xr netintro 4 , +.Xr ng_ether 4 , +.Xr ifconfig 8 +.Sh HISTORY +The +.Nm +device driver first appeared in +.Fx 12.0 . +.Sh AUTHORS +.An -nosplit +The +.Nm +driver was written by +.An David C Somayajulu +at Cavium Inc. Modified: head/sys/conf/files.amd64 ============================================================================== --- head/sys/conf/files.amd64 Tue Apr 4 05:56:42 2017 (r316484) +++ head/sys/conf/files.amd64 Tue Apr 4 06:16:59 2017 (r316485) @@ -364,6 +364,20 @@ dev/qlxgbe/ql_isr.c optional qlxgbe pci dev/qlxgbe/ql_misc.c optional qlxgbe pci dev/qlxgbe/ql_os.c optional qlxgbe pci dev/qlxgbe/ql_reset.c optional qlxgbe pci +dev/qlnx/qlnxe/ecore_cxt.c optional qlnxe pci +dev/qlnx/qlnxe/ecore_dbg_fw_funcs.c optional qlnxe pci +dev/qlnx/qlnxe/ecore_dcbx.c optional qlnxe pci +dev/qlnx/qlnxe/ecore_dev.c optional qlnxe pci +dev/qlnx/qlnxe/ecore_hw.c optional qlnxe pci +dev/qlnx/qlnxe/ecore_init_fw_funcs.c optional qlnxe pci +dev/qlnx/qlnxe/ecore_init_ops.c optional qlnxe pci +dev/qlnx/qlnxe/ecore_int.c optional qlnxe pci +dev/qlnx/qlnxe/ecore_l2.c optional qlnxe pci +dev/qlnx/qlnxe/ecore_mcp.c optional qlnxe pci +dev/qlnx/qlnxe/ecore_sp_commands.c optional qlnxe pci +dev/qlnx/qlnxe/ecore_spq.c optional qlnxe pci +dev/qlnx/qlnxe/qlnx_ioctl.c optional qlnxe pci +dev/qlnx/qlnxe/qlnx_os.c optional qlnxe pci dev/sfxge/common/ef10_ev.c optional sfxge pci dev/sfxge/common/ef10_filter.c optional sfxge pci dev/sfxge/common/ef10_intr.c optional sfxge pci Added: head/sys/dev/qlnx/qlnxe/bcm_osal.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/sys/dev/qlnx/qlnxe/bcm_osal.h Tue Apr 4 06:16:59 2017 (r316485) @@ -0,0 +1,527 @@ +/* + * Copyright (c) 2017-2018 Cavium, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef __BCM_OSAL_ECORE_PACKAGE +#define __BCM_OSAL_ECORE_PACKAGE + +#include "qlnx_os.h" +#include "ecore_status.h" +#include <sys/bitstring.h> + +#if __FreeBSD_version >= 1100090 +#include <compat/linuxkpi/common/include/linux/bitops.h> +#else +#include <ofed/include/linux/bitops.h> +#endif + +/* + * prototypes of freebsd specific functions required by ecore + */ +extern uint32_t qlnx_pci_bus_get_bar_size(void *ecore_dev, uint8_t bar_id); +extern uint32_t qlnx_pci_read_config_byte(void *ecore_dev, uint32_t pci_reg, + uint8_t *reg_value); +extern uint32_t qlnx_pci_read_config_word(void *ecore_dev, uint32_t pci_reg, + uint16_t *reg_value); +extern uint32_t qlnx_pci_read_config_dword(void *ecore_dev, uint32_t pci_reg, + uint32_t *reg_value); +extern void qlnx_pci_write_config_byte(void *ecore_dev, uint32_t pci_reg, + uint8_t reg_value); +extern void qlnx_pci_write_config_word(void *ecore_dev, uint32_t pci_reg, + uint16_t reg_value); +extern void qlnx_pci_write_config_dword(void *ecore_dev, uint32_t pci_reg, + uint32_t reg_value); +extern int qlnx_pci_find_capability(void *ecore_dev, int cap); + +extern uint32_t qlnx_direct_reg_rd32(void *p_hwfn, uint32_t *reg_addr); +extern void qlnx_direct_reg_wr32(void *p_hwfn, void *reg_addr, uint32_t value); + +extern uint32_t qlnx_reg_rd32(void *p_hwfn, uint32_t reg_addr); +extern void qlnx_reg_wr32(void *p_hwfn, uint32_t reg_addr, uint32_t value); +extern void qlnx_reg_wr16(void *p_hwfn, uint32_t reg_addr, uint16_t value); + +extern void qlnx_dbell_wr32(void *p_hwfn, uint32_t reg_addr, uint32_t value); + +extern void *qlnx_dma_alloc_coherent(void *ecore_dev, bus_addr_t *phys, + uint32_t size); +extern void qlnx_dma_free_coherent(void *ecore_dev, void *v_addr, + bus_addr_t phys, uint32_t size); + +extern void qlnx_link_update(void *p_hwfn); +extern void qlnx_barrier(void *p_hwfn); + +extern void *qlnx_zalloc(uint32_t size); + +extern void qlnx_get_protocol_stats(void *cdev, int proto_type, + void *proto_stats); + +extern void qlnx_sp_isr(void *arg); + + +#ifdef ECORE_PACKAGE + +/* Memory Types */ +#define u8 uint8_t +#define u16 uint16_t +#define u32 uint32_t +#define u64 uint64_t +#define s16 uint16_t +#define s32 uint32_t + +#ifndef QLNX_RDMA + +typedef uint16_t __le16; +typedef uint32_t __le32; +typedef uint16_t __be16; +typedef uint32_t __be32; + +static __inline unsigned long +roundup_pow_of_two(unsigned long x) +{ + return (1UL << flsl(x - 1)); +} + +static __inline int +is_power_of_2(unsigned long n) +{ + return (n == roundup_pow_of_two(n)); +} + +static __inline unsigned long +rounddown_pow_of_two(unsigned long x) +{ + return (1UL << (flsl(x) - 1)); +} + +#define max_t(type, val1, val2) \ + ((type)(val1) > (type)(val2) ? (type)(val1) : (val2)) +#define min_t(type, val1, val2) \ + ((type)(val1) < (type)(val2) ? (type)(val1) : (val2)) + +#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof(arr[0])) +#define nothing do {} while(0) +#define BUILD_BUG_ON(cond) nothing + +#endif /* #ifndef QLNX_RDMA */ + +#define OSAL_CPU_TO_BE64(val) htobe64(val) +#define OSAL_BE64_TO_CPU(val) be64toh(val) + +#define OSAL_CPU_TO_BE32(val) htobe32(val) +#define OSAL_BE32_TO_CPU(val) be32toh(val) + +#define OSAL_CPU_TO_LE32(val) htole32(val) +#define OSAL_LE32_TO_CPU(val) le32toh(val) + +#define OSAL_CPU_TO_BE16(val) htobe16(val) +#define OSAL_BE16_TO_CPU(val) be16toh(val) + +#define OSAL_CPU_TO_LE16(val) htole16(val) +#define OSAL_LE16_TO_CPU(val) le16toh(val) + +#define OSAL_CACHE_LINE_SIZE CACHE_LINE_SIZE +#define OSAL_BE32 uint32_t +#define dma_addr_t bus_addr_t +#define osal_size_t size_t + +typedef struct mtx osal_spinlock_t; +typedef struct mtx osal_mutex_t; + +typedef void * osal_dpc_t; + +typedef struct _osal_list_entry_t +{ + struct _osal_list_entry_t *next, *prev; +} osal_list_entry_t; + +typedef struct osal_list_t +{ + osal_list_entry_t *head, *tail; + unsigned long cnt; +} osal_list_t; + +/* OSAL functions */ + +#define OSAL_UDELAY(time) DELAY(time) +#define OSAL_MSLEEP(time) qlnx_mdelay(__func__, time) + +#define OSAL_ALLOC(dev, GFP, size) qlnx_zalloc(size) +#define OSAL_ZALLOC(dev, GFP, size) qlnx_zalloc(size) +#define OSAL_VALLOC(dev, size) qlnx_zalloc(size) +#define OSAL_VZALLOC(dev, size) qlnx_zalloc(size) + +#define OSAL_FREE(dev, memory) free(memory, M_QLNXBUF) +#define OSAL_VFREE(dev, memory) free(memory, M_QLNXBUF) + +#define OSAL_MEM_ZERO(mem, size) bzero(mem, size) + +#define OSAL_MEMCPY(dst, src, size) memcpy(dst, src, size) + +#define OSAL_DMA_ALLOC_COHERENT(dev, phys, size) \ + qlnx_dma_alloc_coherent(dev, phys, size) + +#define OSAL_DMA_FREE_COHERENT(dev, virt, phys, size) \ + qlnx_dma_free_coherent(dev, virt, phys, size) +#define OSAL_VF_CQE_COMPLETION(_dev_p, _cqe, _protocol) (0) + +#define REG_WR(hwfn, addr, val) qlnx_reg_wr32(hwfn, addr, val) +#define REG_WR16(hwfn, addr, val) qlnx_reg_wr16(hwfn, addr, val) +#define DIRECT_REG_WR(p_hwfn, addr, value) qlnx_direct_reg_wr32(p_hwfn, addr, value) +#define DIRECT_REG_RD(p_hwfn, addr) qlnx_direct_reg_rd32(p_hwfn, addr) +#define REG_RD(hwfn, addr) qlnx_reg_rd32(hwfn, addr) +#define DOORBELL(hwfn, addr, value) \ + qlnx_dbell_wr32(hwfn, addr, value) + +#define OSAL_SPIN_LOCK_ALLOC(p_hwfn, mutex) +#define OSAL_SPIN_LOCK_DEALLOC(mutex) mtx_destroy(mutex) +#define OSAL_SPIN_LOCK_INIT(lock) {\ + mtx_init(lock, __func__, MTX_NETWORK_LOCK, MTX_SPIN); \ + } + +#define OSAL_SPIN_UNLOCK(lock) {\ + mtx_unlock(lock); \ + } +#define OSAL_SPIN_LOCK(lock) {\ + mtx_lock(lock); \ + } + +#define OSAL_MUTEX_ALLOC(p_hwfn, mutex) +#define OSAL_MUTEX_DEALLOC(mutex) mtx_destroy(mutex) +#define OSAL_MUTEX_INIT(lock) {\ + mtx_init(lock, __func__, MTX_NETWORK_LOCK, MTX_DEF);\ + } + +#define OSAL_MUTEX_ACQUIRE(lock) mtx_lock(lock) +#define OSAL_MUTEX_RELEASE(lock) mtx_unlock(lock) + +#define OSAL_DPC_ALLOC(hwfn) malloc(PAGE_SIZE, M_QLNXBUF, M_NOWAIT) +#define OSAL_DPC_INIT(dpc, hwfn) nothing +#define OSAL_SCHEDULE_RECOVERY_HANDLER(x) nothing +#define OSAL_HW_ERROR_OCCURRED(hwfn, err_type) nothing +#define OSAL_DPC_SYNC(hwfn) nothing + +static inline void OSAL_DCBX_AEN(void *p_hwfn, u32 mib_type) +{ + return; +} + +static inline bool OSAL_NVM_IS_ACCESS_ENABLED(void *p_hwfn) +{ + return 1; +} + +#define OSAL_LIST_INIT(list) \ + do { \ + (list)->head = NULL; \ + (list)->tail = NULL; \ + (list)->cnt = 0; \ + } while (0) + +#define OSAL_LIST_INSERT_ENTRY_AFTER(entry, entry_prev, list) \ +do { \ + (entry)->prev = (entry_prev); \ + (entry)->next = (entry_prev)->next; \ + (entry)->next->prev = (entry); \ + (entry_prev)->next = (entry); \ + (list)->cnt++; \ +} while (0); + +#define OSAL_LIST_SPLICE_TAIL_INIT(new_list, list) \ +do { \ + ((new_list)->tail)->next = ((list)->head); \ + ((list)->head)->prev = ((new_list)->tail); \ + (list)->head = (new_list)->head; \ + (list)->cnt = (list)->cnt + (new_list)->cnt; \ + OSAL_LIST_INIT(new_list); \ +} while (0); + +#define OSAL_LIST_PUSH_HEAD(entry, list) \ + do { \ + (entry)->prev = (osal_list_entry_t *)0; \ + (entry)->next = (list)->head; \ + if ((list)->tail == (osal_list_entry_t *)0) { \ + (list)->tail = (entry); \ + } else { \ + (list)->head->prev = (entry); \ + } \ + (list)->head = (entry); \ + (list)->cnt++; \ + } while (0) + +#define OSAL_LIST_PUSH_TAIL(entry, list) \ + do { \ + (entry)->next = (osal_list_entry_t *)0; \ + (entry)->prev = (list)->tail; \ + if ((list)->tail) { \ + (list)->tail->next = (entry); \ + } else { \ + (list)->head = (entry); \ + } \ + (list)->tail = (entry); \ + (list)->cnt++; \ + } while (0) + +#define OSAL_LIST_FIRST_ENTRY(list, type, field) \ + (type *)((list)->head) + +#define OSAL_LIST_REMOVE_ENTRY(entry, list) \ + do { \ + if ((list)->head == (entry)) { \ + if ((list)->head) { \ + (list)->head = (list)->head->next; \ + if ((list)->head) { \ + (list)->head->prev = (osal_list_entry_t *)0; \ + } else { \ + (list)->tail = (osal_list_entry_t *)0; \ + } \ + (list)->cnt--; \ + } \ + } else if ((list)->tail == (entry)) { \ + if ((list)->tail) { \ + (list)->tail = (list)->tail->prev; \ + if ((list)->tail) { \ + (list)->tail->next = (osal_list_entry_t *)0; \ + } else { \ + (list)->head = (osal_list_entry_t *)0; \ + } \ + (list)->cnt--; \ + } \ + } else { \ + (entry)->prev->next = (entry)->next; \ + (entry)->next->prev = (entry)->prev; \ + (list)->cnt--; \ + } \ + } while (0) + + +#define OSAL_LIST_IS_EMPTY(list) \ + ((list)->cnt == 0) + +#define OSAL_LIST_NEXT(entry, field, type) \ + (type *)((&((entry)->field))->next) + +#define OSAL_LIST_FOR_EACH_ENTRY(entry, list, field, type) \ + for (entry = OSAL_LIST_FIRST_ENTRY(list, type, field); \ + entry; \ + entry = OSAL_LIST_NEXT(entry, field, type)) + +#define OSAL_LIST_FOR_EACH_ENTRY_SAFE(entry, tmp_entry, list, field, type) \ + for (entry = OSAL_LIST_FIRST_ENTRY(list, type, field), \ + tmp_entry = (entry) ? OSAL_LIST_NEXT(entry, field, type) : NULL; \ + entry != NULL; \ + entry = (type *)tmp_entry, \ + tmp_entry = (entry) ? OSAL_LIST_NEXT(entry, field, type) : NULL) + + +#define OSAL_BAR_SIZE(dev, bar_id) qlnx_pci_bus_get_bar_size(dev, bar_id) + +#define OSAL_PCI_READ_CONFIG_BYTE(dev, reg, value) \ + qlnx_pci_read_config_byte(dev, reg, value); +#define OSAL_PCI_READ_CONFIG_WORD(dev, reg, value) \ + qlnx_pci_read_config_word(dev, reg, value); +#define OSAL_PCI_READ_CONFIG_DWORD(dev, reg, value) \ + qlnx_pci_read_config_dword(dev, reg, value); + +#define OSAL_PCI_WRITE_CONFIG_BYTE(dev, reg, value) \ + qlnx_pci_write_config_byte(dev, reg, value); +#define OSAL_PCI_WRITE_CONFIG_WORD(dev, reg, value) \ + qlnx_pci_write_config_word(dev, reg, value); +#define OSAL_PCI_WRITE_CONFIG_DWORD(dev, reg, value) \ + qlnx_pci_write_config_dword(dev, reg, value); + +#define OSAL_PCI_FIND_CAPABILITY(dev, cap) qlnx_pci_find_capability(dev, cap); + +#define OSAL_MMIOWB(dev) qlnx_barrier(dev) +#define OSAL_BARRIER(dev) qlnx_barrier(dev) + +#define OSAL_SMP_MB(dev) mb() +#define OSAL_SMP_RMB(dev) rmb() +#define OSAL_SMP_WMB(dev) wmb() +#define OSAL_RMB(dev) rmb() +#define OSAL_WMB(dev) wmb() +#define OSAL_DMA_SYNC(dev, addr, length, is_post) + +#define OSAL_FIND_FIRST_BIT find_first_bit +#define OSAL_SET_BIT(bit, bitmap) bit_set((bitstr_t *)bitmap, bit) +#define OSAL_CLEAR_BIT(bit, bitmap) bit_clear((bitstr_t *)bitmap, bit) +#define OSAL_TEST_BIT(bit, bitmap) bit_test((bitstr_t *)bitmap, bit) +#define OSAL_FIND_FIRST_ZERO_BIT(bitmap, length) \ + find_first_zero_bit(bitmap, length) + +#define OSAL_LINK_UPDATE(hwfn) qlnx_link_update(hwfn) +#define OSAL_VF_FLR_UPDATE(hwfn) + +#define QLNX_DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) +#define QLNX_ROUNDUP(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) + +#define OSAL_NUM_ACTIVE_CPU() mp_ncpus + +#ifndef DIV_ROUND_UP +#define DIV_ROUND_UP(size, to_what) QLNX_DIV_ROUND_UP((size), (to_what)) +#endif + +#define ROUNDUP(value, to_what) QLNX_ROUNDUP((value), (to_what)) + +#define OSAL_ROUNDUP_POW_OF_TWO(val) roundup_pow_of_two((val)) + +static __inline uint32_t +qlnx_log2(uint32_t x) +{ + uint32_t log = 0; + + while (x >>= 1) log++; + + return (log); +} + +#define OSAL_LOG2(val) qlnx_log2(val) +#define OFFSETOF(str, field) offsetof(str, field) +#define PRINT device_printf +#define PRINT_ERR device_printf +#define OSAL_ASSERT(is_assert) nothing +#define OSAL_BEFORE_PF_START(cdev, my_id) {}; +#define OSAL_AFTER_PF_STOP(cdev, my_id) {}; + +#define INLINE __inline +#define OSAL_INLINE __inline +#define OSAL_UNLIKELY +#define OSAL_NULL NULL + + +#define OSAL_MAX_T(type, __max1, __max2) max_t(type, __max1, __max2) +#define OSAL_MIN_T(type, __max1, __max2) min_t(type, __max1, __max2) + +#define __iomem +#define OSAL_IOMEM + +#define int_ptr_t void * +#define osal_int_ptr_t void * +#define OSAL_BUILD_BUG_ON(cond) nothing +#define REG_ADDR(hwfn, offset) (void *)((u8 *)(hwfn->regview) + (offset)) +#define OSAL_REG_ADDR(hwfn, offset) (void *)((u8 *)(hwfn->regview) + (offset)) + +#define OSAL_PAGE_SIZE PAGE_SIZE + +#define OSAL_STRCPY(dst, src) strcpy(dst, src) +#define OSAL_STRNCPY(dst, src, bytes) strncpy(dst, src, bytes) +#define OSAL_STRLEN(src) strlen(src) +#define OSAL_SPRINTF sprintf +#define OSAL_SNPRINTF snprintf +#define OSAL_MEMSET memset +#define OSAL_ARRAY_SIZE(arr) (sizeof(arr) / sizeof(arr[0])) +#define osal_uintptr_t u64 + +#define OSAL_SLOWPATH_IRQ_REQ(p_hwfn) (0) +#define OSAL_GET_PROTOCOL_STATS(p_hwfn, type, stats) \ + qlnx_get_protocol_stats(p_hwfn, type, stats); +#define OSAL_POLL_MODE_DPC(hwfn) {if (cold) qlnx_sp_isr(hwfn);} +#define OSAL_WARN(cond, fmt, args...) \ + if (cond) printf("%s: WARNING: " fmt, __func__, ## args); + +#define OSAL_BITMAP_WEIGHT(bitmap, nbits) bitmap_weight(bitmap, nbits) +#define OSAL_GET_RDMA_SB_ID(p_hwfn, cnq_id) ecore_rdma_get_sb_id(p_hwfn, cnq_id) + +static inline int +qlnx_test_and_change_bit(long bit, volatile unsigned long *var) +{ + long val; + + var += BIT_WORD(bit); + bit %= BITS_PER_LONG; + bit = (1UL << bit); + + val = *var; + +#if __FreeBSD_version >= 1100000 + if (val & bit) + return (test_and_clear_bit(bit, var)); + + return (test_and_set_bit(bit, var)); +#else + if (val & bit) + return (test_and_clear_bit(bit, (long *)var)); + + return (test_and_set_bit(bit, (long *)var)); + +#endif +} + +#if __FreeBSD_version < 1100000 +static inline unsigned +bitmap_weight(unsigned long *bitmap, unsigned nbits) +{ + unsigned bit; + unsigned retval = 0; + + for_each_set_bit(bit, bitmap, nbits) + retval++; + return (retval); +} + +#endif + + +#define OSAL_TEST_AND_FLIP_BIT qlnx_test_and_change_bit +#define OSAL_TEST_AND_CLEAR_BIT test_and_clear_bit +#define OSAL_MEMCMP memcmp +#define OSAL_SPIN_LOCK_IRQSAVE(x,y) {y=0; mtx_lock(x);} +#define OSAL_SPIN_UNLOCK_IRQSAVE(x,y) {y= 0; mtx_unlock(x);} + +static inline u32 +OSAL_CRC32(u32 crc, u8 *ptr, u32 length) +{ + int i; + + while (length--) { + crc ^= *ptr++; + for (i = 0; i < 8; i++) + crc = (crc >> 1) ^ ((crc & 1) ? 0xedb88320 : 0); + } + return crc; +} + +static inline void +OSAL_CRC8_POPULATE(u8 * cdu_crc8_table, u8 polynomial) +{ + return; +} + +static inline u8 +OSAL_CRC8(u8 * cdu_crc8_table, u8 * data_to_crc, int data_to_crc_len, u8 init_value) +{ + return ECORE_NOTIMPL; +} + +#define OSAL_HW_INFO_CHANGE(p_hwfn, offset) +#define OSAL_MFW_TLV_REQ(p_hwfn) +#define OSAL_VF_FILL_ACQUIRE_RESC_REQ(p_hwfn, req, vf_sw_info) {}; +#define OSAL_VF_UPDATE_ACQUIRE_RESC_RESP(p_hwfn, res) (0) + +#endif /* #ifdef ECORE_PACKAGE */ + +#endif /* #ifdef __BCM_OSAL_ECORE_PACKAGE */ Added: head/sys/dev/qlnx/qlnxe/common_hsi.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/sys/dev/qlnx/qlnxe/common_hsi.h Tue Apr 4 06:16:59 2017 (r316485) @@ -0,0 +1,1589 @@ +/* + * Copyright (c) 2017-2018 Cavium, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + * + */ + +#ifndef __COMMON_HSI__ +#define __COMMON_HSI__ +/********************************/ +/* PROTOCOL COMMON FW CONSTANTS */ +/********************************/ + +/* Temporarily here should be added to HSI automatically by resource allocation tool.*/ +#define T_TEST_AGG_INT_TEMP 6 +#define M_TEST_AGG_INT_TEMP 8 +#define U_TEST_AGG_INT_TEMP 6 +#define X_TEST_AGG_INT_TEMP 14 +#define Y_TEST_AGG_INT_TEMP 4 +#define P_TEST_AGG_INT_TEMP 4 + +#define X_FINAL_CLEANUP_AGG_INT 1 + +#define EVENT_RING_PAGE_SIZE_BYTES 4096 + +#define NUM_OF_GLOBAL_QUEUES 128 +#define COMMON_QUEUE_ENTRY_MAX_BYTE_SIZE 64 + +#define ISCSI_CDU_TASK_SEG_TYPE 0 +#define FCOE_CDU_TASK_SEG_TYPE 0 +#define RDMA_CDU_TASK_SEG_TYPE 1 + +#define FW_ASSERT_GENERAL_ATTN_IDX 32 + +#define MAX_PINNED_CCFC 32 + +#define EAGLE_ENG1_WORKAROUND_NIG_FLOWCTRL_MODE 3 + +/* Queue Zone sizes in bytes */ +#define TSTORM_QZONE_SIZE 8 /*tstorm_scsi_queue_zone*/ +#define MSTORM_QZONE_SIZE 16 /*mstorm_eth_queue_zone. Used only for RX producer of VFs in backward compatibility mode.*/ +#define USTORM_QZONE_SIZE 8 /*ustorm_eth_queue_zone*/ +#define XSTORM_QZONE_SIZE 8 /*xstorm_eth_queue_zone*/ +#define YSTORM_QZONE_SIZE 0 +#define PSTORM_QZONE_SIZE 0 + +#define MSTORM_VF_ZONE_DEFAULT_SIZE_LOG 7 /*Log of mstorm default VF zone size.*/ +#define ETH_MAX_NUM_RX_QUEUES_PER_VF_DEFAULT 16 /*Maximum number of RX queues that can be allocated to VF by default*/ +#define ETH_MAX_NUM_RX_QUEUES_PER_VF_DOUBLE 48 /*Maximum number of RX queues that can be allocated to VF with doubled VF zone size. Up to 96 VF supported in this mode*/ +#define ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD 112 /*Maximum number of RX queues that can be allocated to VF with 4 VF zone size. Up to 48 VF supported in this mode*/ + + +/********************************/ +/* CORE (LIGHT L2) FW CONSTANTS */ +/********************************/ + +#define CORE_LL2_MAX_RAMROD_PER_CON 8 +#define CORE_LL2_TX_BD_PAGE_SIZE_BYTES 4096 +#define CORE_LL2_RX_BD_PAGE_SIZE_BYTES 4096 +#define CORE_LL2_RX_CQE_PAGE_SIZE_BYTES 4096 +#define CORE_LL2_RX_NUM_NEXT_PAGE_BDS 1 + +#define CORE_LL2_TX_MAX_BDS_PER_PACKET 12 + +#define CORE_SPQE_PAGE_SIZE_BYTES 4096 + +/* + * Usually LL2 queues are opened in pairs TX-RX. + * There is a hard restriction on number of RX queues (limited by Tstorm RAM) and TX counters (Pstorm RAM). + * Number of TX queues is almost unlimited. + * The constants are different so as to allow asymmetric LL2 connections + */ + +#define MAX_NUM_LL2_RX_QUEUES 48 +#define MAX_NUM_LL2_TX_STATS_COUNTERS 48 + + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// Include firmware version number only- do not add constants here to avoid redundunt compilations +/////////////////////////////////////////////////////////////////////////////////////////////////// + + +#define FW_MAJOR_VERSION 8 +#define FW_MINOR_VERSION 18 +#define FW_REVISION_VERSION 14 +#define FW_ENGINEERING_VERSION 0 + +/***********************/ +/* COMMON HW CONSTANTS */ +/***********************/ + +/* PCI functions */ +#define MAX_NUM_PORTS_K2 (4) +#define MAX_NUM_PORTS_BB (2) +#define MAX_NUM_PORTS (MAX_NUM_PORTS_K2) + +#define MAX_NUM_PFS_K2 (16) +#define MAX_NUM_PFS_BB (8) +#define MAX_NUM_PFS (MAX_NUM_PFS_K2) +#define MAX_NUM_OF_PFS_IN_CHIP (16) /* On both engines */ + +#define MAX_NUM_VFS_BB (120) +#define MAX_NUM_VFS_K2 (192) +#define E4_MAX_NUM_VFS (MAX_NUM_VFS_K2) +#define E5_MAX_NUM_VFS (240) +#define COMMON_MAX_NUM_VFS (E5_MAX_NUM_VFS) + +#define MAX_NUM_FUNCTIONS_BB (MAX_NUM_PFS_BB + MAX_NUM_VFS_BB) +#define MAX_NUM_FUNCTIONS_K2 (MAX_NUM_PFS_K2 + MAX_NUM_VFS_K2) +#define MAX_NUM_FUNCTIONS (MAX_NUM_PFS + E4_MAX_NUM_VFS) + +/* in both BB and K2, the VF number starts from 16. so for arrays containing all */ +/* possible PFs and VFs - we need a constant for this size */ +#define MAX_FUNCTION_NUMBER_BB (MAX_NUM_PFS + MAX_NUM_VFS_BB) +#define MAX_FUNCTION_NUMBER_K2 (MAX_NUM_PFS + MAX_NUM_VFS_K2) +#define MAX_FUNCTION_NUMBER (MAX_NUM_PFS + E4_MAX_NUM_VFS) + +#define MAX_NUM_VPORTS_K2 (208) +#define MAX_NUM_VPORTS_BB (160) +#define MAX_NUM_VPORTS (MAX_NUM_VPORTS_K2) + +#define MAX_NUM_L2_QUEUES_K2 (320) +#define MAX_NUM_L2_QUEUES_BB (256) +#define MAX_NUM_L2_QUEUES (MAX_NUM_L2_QUEUES_K2) + +/* Traffic classes in network-facing blocks (PBF, BTB, NIG, BRB, PRS and QM) */ +// 4-Port K2. +#define NUM_PHYS_TCS_4PORT_K2 (4) +#define NUM_OF_PHYS_TCS (8) + +#define NUM_TCS_4PORT_K2 (NUM_PHYS_TCS_4PORT_K2 + 1) +#define NUM_OF_TCS (NUM_OF_PHYS_TCS + 1) + +#define LB_TC (NUM_OF_PHYS_TCS) + +/* Num of possible traffic priority values */ +#define NUM_OF_PRIO (8) + +#define MAX_NUM_VOQS_K2 (NUM_TCS_4PORT_K2 * MAX_NUM_PORTS_K2) +#define MAX_NUM_VOQS_BB (NUM_OF_TCS * MAX_NUM_PORTS_BB) +#define MAX_NUM_VOQS (MAX_NUM_VOQS_K2) +#define MAX_PHYS_VOQS (NUM_OF_PHYS_TCS * MAX_NUM_PORTS_BB) + +/* CIDs */ +#define E4_NUM_OF_CONNECTION_TYPES (8) +#define E5_NUM_OF_CONNECTION_TYPES (16) +#define NUM_OF_TASK_TYPES (8) +#define NUM_OF_LCIDS (320) +#define NUM_OF_LTIDS (320) + +/* Clock values */ +#define MASTER_CLK_FREQ_E4 (375e6) +#define STORM_CLK_FREQ_E4 (1000e6) +#define CLK25M_CLK_FREQ_E4 (25e6) + +#define STORM_CLK_DUAL_CORE_FREQ_E5 (3000e6) + +/* Global PXP windows (GTT) */ +#define NUM_OF_GTT 19 +#define GTT_DWORD_SIZE_BITS 10 +#define GTT_BYTE_SIZE_BITS (GTT_DWORD_SIZE_BITS + 2) +#define GTT_DWORD_SIZE (1 << GTT_DWORD_SIZE_BITS) + +/* Tools Version */ +#define TOOLS_VERSION 10 +/*****************/ +/* CDU CONSTANTS */ +/*****************/ + +#define CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (17) +#define CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0x1ffff) + +#define CDU_VF_FL_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (12) +#define CDU_VF_FL_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0xfff) + +#define CDU_CONTEXT_VALIDATION_CFG_ENABLE_SHIFT (0) +#define CDU_CONTEXT_VALIDATION_CFG_VALIDATION_TYPE_SHIFT (1) +#define CDU_CONTEXT_VALIDATION_CFG_USE_TYPE (2) +#define CDU_CONTEXT_VALIDATION_CFG_USE_REGION (3) +#define CDU_CONTEXT_VALIDATION_CFG_USE_CID (4) +#define CDU_CONTEXT_VALIDATION_CFG_USE_ACTIVE (5) + + +/*****************/ +/* DQ CONSTANTS */ +/*****************/ + +/* DEMS */ +#define DQ_DEMS_LEGACY 0 +#define DQ_DEMS_TOE_MORE_TO_SEND 3 +#define DQ_DEMS_TOE_LOCAL_ADV_WND 4 +#define DQ_DEMS_ROCE_CQ_CONS 7 + +/* XCM agg val selection (HW) */ +#define DQ_XCM_AGG_VAL_SEL_WORD2 0 +#define DQ_XCM_AGG_VAL_SEL_WORD3 1 +#define DQ_XCM_AGG_VAL_SEL_WORD4 2 +#define DQ_XCM_AGG_VAL_SEL_WORD5 3 +#define DQ_XCM_AGG_VAL_SEL_REG3 4 +#define DQ_XCM_AGG_VAL_SEL_REG4 5 +#define DQ_XCM_AGG_VAL_SEL_REG5 6 +#define DQ_XCM_AGG_VAL_SEL_REG6 7 + +/* XCM agg val selection (FW) */ +#define DQ_XCM_CORE_TX_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 +#define DQ_XCM_CORE_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 +#define DQ_XCM_CORE_SPQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 +#define DQ_XCM_ETH_EDPM_NUM_BDS_CMD DQ_XCM_AGG_VAL_SEL_WORD2 +#define DQ_XCM_ETH_TX_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 +#define DQ_XCM_ETH_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 +#define DQ_XCM_ETH_GO_TO_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD5 +#define DQ_XCM_FCOE_SQ_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 +#define DQ_XCM_FCOE_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 +#define DQ_XCM_FCOE_X_FERQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD5 +#define DQ_XCM_ISCSI_SQ_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 +#define DQ_XCM_ISCSI_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 +#define DQ_XCM_ISCSI_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3 +#define DQ_XCM_ISCSI_EXP_STAT_SN_CMD DQ_XCM_AGG_VAL_SEL_REG6 +#define DQ_XCM_ROCE_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 +#define DQ_XCM_TOE_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 +#define DQ_XCM_TOE_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3 +#define DQ_XCM_TOE_LOCAL_ADV_WND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG4 + +/* UCM agg val selection (HW) */ +#define DQ_UCM_AGG_VAL_SEL_WORD0 0 +#define DQ_UCM_AGG_VAL_SEL_WORD1 1 +#define DQ_UCM_AGG_VAL_SEL_WORD2 2 +#define DQ_UCM_AGG_VAL_SEL_WORD3 3 +#define DQ_UCM_AGG_VAL_SEL_REG0 4 +#define DQ_UCM_AGG_VAL_SEL_REG1 5 +#define DQ_UCM_AGG_VAL_SEL_REG2 6 +#define DQ_UCM_AGG_VAL_SEL_REG3 7 + +/* UCM agg val selection (FW) */ +#define DQ_UCM_ETH_PMD_TX_CONS_CMD DQ_UCM_AGG_VAL_SEL_WORD2 +#define DQ_UCM_ETH_PMD_RX_CONS_CMD DQ_UCM_AGG_VAL_SEL_WORD3 +#define DQ_UCM_ROCE_CQ_CONS_CMD DQ_UCM_AGG_VAL_SEL_REG0 +#define DQ_UCM_ROCE_CQ_PROD_CMD DQ_UCM_AGG_VAL_SEL_REG2 + +/* TCM agg val selection (HW) */ +#define DQ_TCM_AGG_VAL_SEL_WORD0 0 +#define DQ_TCM_AGG_VAL_SEL_WORD1 1 +#define DQ_TCM_AGG_VAL_SEL_WORD2 2 +#define DQ_TCM_AGG_VAL_SEL_WORD3 3 +#define DQ_TCM_AGG_VAL_SEL_REG1 4 +#define DQ_TCM_AGG_VAL_SEL_REG2 5 +#define DQ_TCM_AGG_VAL_SEL_REG6 6 +#define DQ_TCM_AGG_VAL_SEL_REG9 7 + +/* TCM agg val selection (FW) */ +#define DQ_TCM_L2B_BD_PROD_CMD DQ_TCM_AGG_VAL_SEL_WORD1 +#define DQ_TCM_ROCE_RQ_PROD_CMD DQ_TCM_AGG_VAL_SEL_WORD0 + +/* XCM agg counter flag selection (HW) */ +#define DQ_XCM_AGG_FLG_SHIFT_BIT14 0 +#define DQ_XCM_AGG_FLG_SHIFT_BIT15 1 +#define DQ_XCM_AGG_FLG_SHIFT_CF12 2 +#define DQ_XCM_AGG_FLG_SHIFT_CF13 3 +#define DQ_XCM_AGG_FLG_SHIFT_CF18 4 +#define DQ_XCM_AGG_FLG_SHIFT_CF19 5 +#define DQ_XCM_AGG_FLG_SHIFT_CF22 6 +#define DQ_XCM_AGG_FLG_SHIFT_CF23 7 + +/* XCM agg counter flag selection (FW) */ +#define DQ_XCM_CORE_DQ_CF_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF18) +#define DQ_XCM_CORE_TERMINATE_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF19) +#define DQ_XCM_CORE_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22) +#define DQ_XCM_ETH_DQ_CF_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF18) +#define DQ_XCM_ETH_TERMINATE_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF19) +#define DQ_XCM_ETH_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22) +#define DQ_XCM_ETH_TPH_EN_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF23) +#define DQ_XCM_FCOE_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22) +#define DQ_XCM_ISCSI_DQ_FLUSH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF19) +#define DQ_XCM_ISCSI_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22) +#define DQ_XCM_ISCSI_PROC_ONLY_CLEANUP_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF23) +#define DQ_XCM_TOE_DQ_FLUSH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF19) +#define DQ_XCM_TOE_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22) + +/* UCM agg counter flag selection (HW) */ +#define DQ_UCM_AGG_FLG_SHIFT_CF0 0 +#define DQ_UCM_AGG_FLG_SHIFT_CF1 1 +#define DQ_UCM_AGG_FLG_SHIFT_CF3 2 +#define DQ_UCM_AGG_FLG_SHIFT_CF4 3 +#define DQ_UCM_AGG_FLG_SHIFT_CF5 4 +#define DQ_UCM_AGG_FLG_SHIFT_CF6 5 +#define DQ_UCM_AGG_FLG_SHIFT_RULE0EN 6 +#define DQ_UCM_AGG_FLG_SHIFT_RULE1EN 7 + +/* UCM agg counter flag selection (FW) */ +#define DQ_UCM_ETH_PMD_TX_ARM_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF4) +#define DQ_UCM_ETH_PMD_RX_ARM_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF5) +#define DQ_UCM_ROCE_CQ_ARM_SE_CF_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF4) +#define DQ_UCM_ROCE_CQ_ARM_CF_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF5) +#define DQ_UCM_TOE_TIMER_STOP_ALL_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF3) +#define DQ_UCM_TOE_SLOW_PATH_CF_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF4) +#define DQ_UCM_TOE_DQ_CF_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF5) + +/* TCM agg counter flag selection (HW) */ +#define DQ_TCM_AGG_FLG_SHIFT_CF0 0 +#define DQ_TCM_AGG_FLG_SHIFT_CF1 1 +#define DQ_TCM_AGG_FLG_SHIFT_CF2 2 +#define DQ_TCM_AGG_FLG_SHIFT_CF3 3 +#define DQ_TCM_AGG_FLG_SHIFT_CF4 4 +#define DQ_TCM_AGG_FLG_SHIFT_CF5 5 *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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