Date: Mon, 23 May 2011 19:58:08 +0000 (UTC) From: Pyun YongHyeon <yongari@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r222219 - head/sys/dev/msk Message-ID: <201105231958.p4NJw8B5035430@svn.freebsd.org>
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Author: yongari Date: Mon May 23 19:58:08 2011 New Revision: 222219 URL: http://svn.freebsd.org/changeset/base/222219 Log: Do not blindly clear entire GPHY control register. It seems some bits of the register is used for other purposes such that clearing these bits resulted in unexpected results such as corrupted RX frames or missing LE status updates. For old controllers like Yukon EC it had no effect but it caused all kind of troubles on Yukon Supreme. This change shall improve stability of controllers like Yukon Ultra, Ultra2, Extreme, Optima and Supreme. Modified: head/sys/dev/msk/if_msk.c Modified: head/sys/dev/msk/if_msk.c ============================================================================== --- head/sys/dev/msk/if_msk.c Mon May 23 19:57:12 2011 (r222218) +++ head/sys/dev/msk/if_msk.c Mon May 23 19:58:08 2011 (r222219) @@ -1362,8 +1362,8 @@ mskc_reset(struct msk_softc *sc) /* Reset GPHY/GMAC Control */ for (i = 0; i < sc->msk_num_port; i++) { /* GPHY Control reset. */ - CSR_WRITE_4(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET); - CSR_WRITE_4(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR); + CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET); + CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR); /* GMAC Control reset. */ CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_SET); CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_CLR);
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