Date: Sun, 20 Jan 2008 22:00:16 GMT From: Warner Losh <imp@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 133744 for review Message-ID: <200801202200.m0KM0Guv015217@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=133744 Change 133744 by imp@imp_paco-paco on 2008/01/20 21:59:51 Select 7 of COP_0's 16th register is not defined by the mips architecture, but reserved for the implementation. In this case, I believe that's because the XLR processor stores its core number in that. For now, comment it all out. Affected files ... .. //depot/projects/mips2-jnpr/src/sys/mips/mips/locore.S#11 edit Differences ... ==== //depot/projects/mips2-jnpr/src/sys/mips/mips/locore.S#11 (text+ko) ==== @@ -163,6 +163,7 @@ no_cfe: #endif +#if 0 /* XXX: this is for the xlr mips CPU */ /* * Block all the slave CPUs */ @@ -178,7 +179,6 @@ /* calculate linear cpuid */ sll t0, a1, 2 addu a2, t0, a0 -#if 0 /* XXX: this is for the xlr mips CPU */ /* Initially, disable all hardware threads on each core except thread0 */ li t1, VCPU_ID_0 li t2, XLR_THREAD_ENABLE_IND @@ -188,10 +188,11 @@ #ifdef SMP la t0, _C_LABEL(__pcpu) SET_CPU_PCPU(t0) -#endif /* If not master cpu, jump... */ +/*XXX this assumes the above #if 0'd code runs */ bne a2, zero, start_secondary nop +#endif /* Call the platform-specific startup code. */ jal platform_start
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