Date: Fri, 30 Jul 1999 02:34:34 -0700 From: Mike Smith <mike@smith.net.au> To: Stephen Hocking-Senior Programmer PGS Tensor Perth <shocking@prth.pgs.com> Cc: current@freebsd.org Subject: Re: MTRR stuff Message-ID: <199907300934.CAA02191@dingo.cdrom.com> In-Reply-To: Your message of "Fri, 09 Jul 1999 10:32:37 %2B0800." <199907090232.KAA04002@ariadne.tensor.pgs.com>
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> For some video cards (to wit, the voodoo stuff), the MTRRs should be set up as > follows > > write-combining > +----------------------------------------------------------+ > +-------+ > uncacheable > > i.e. the two regions have the same starting area, but the small chunk for the > registers should be uncacheable. When I try to do this using memconf on my > K6-2, it spits the dummy. Is there a work around for this? The i686 MTRR implementation, at least, doesn't allow UC to overlap WC; only Write-back and uncached are allowed to overlap. I don't know what the K6's limitations are; you should talk to Brian Feldman about that. -- \\ The mind's the standard \\ Mike Smith \\ of the man. \\ msmith@freebsd.org \\ -- Joseph Merrick \\ msmith@cdrom.com To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-current" in the body of the message
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