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Date:      Sat, 27 Feb 2010 05:46:40 +0000 (UTC)
From:      Juli Mallett <jmallett@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-user@freebsd.org
Subject:   svn commit: r204399 - in user/jmallett/octeon/sys/mips: include mips
Message-ID:  <201002270546.o1R5ke8l069222@svn.freebsd.org>
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Author: jmallett
Date: Sat Feb 27 05:46:40 2010
New Revision: 204399
URL: http://svn.freebsd.org/changeset/base/204399

Log:
  o) Make struct trapdebug use register-width members.
  o) Make trap, which returns the new PC, return a register_t.
  o) Add the two universal cache coherency attributes.

Modified:
  user/jmallett/octeon/sys/mips/include/cpuregs.h
  user/jmallett/octeon/sys/mips/include/trap.h
  user/jmallett/octeon/sys/mips/mips/trap.c

Modified: user/jmallett/octeon/sys/mips/include/cpuregs.h
==============================================================================
--- user/jmallett/octeon/sys/mips/include/cpuregs.h	Sat Feb 27 05:45:32 2010	(r204398)
+++ user/jmallett/octeon/sys/mips/include/cpuregs.h	Sat Feb 27 05:46:40 2010	(r204399)
@@ -96,6 +96,9 @@
 #define	MIPS3_VA_TO_CINDEX(x) \
 		((unsigned)(x) & 0xffffff | MIPS_KSEG0_START)
 
+#define	MIPS_XKPHYS_CCA_UC		0x02	/* Uncached.  */
+#define	MIPS_XKPHYS_CCA_CNC		0x03	/* Cacheable non-coherent.  */
+
 #define	MIPS_PHYS_TO_XKPHYS(cca,x) \
 	((0x2ULL << 62) | ((unsigned long long)(cca) << 59) | (x))
 #define	MIPS_XKPHYS_TO_PHYS(x)	((x) & 0x0effffffffffffffULL)

Modified: user/jmallett/octeon/sys/mips/include/trap.h
==============================================================================
--- user/jmallett/octeon/sys/mips/include/trap.h	Sat Feb 27 05:45:32 2010	(r204398)
+++ user/jmallett/octeon/sys/mips/include/trap.h	Sat Feb 27 05:46:40 2010	(r204399)
@@ -74,13 +74,13 @@
 #if !defined(SMP) && (defined(DDB) || defined(DEBUG))
 
 struct trapdebug {		/* trap history buffer for debugging */
-	u_int	status;
-	u_int	cause;
-	u_int	vadr;
-	u_int	pc;
-	u_int	ra;
-	u_int	sp;
-	u_int	code;
+	register_t	status;
+	register_t	cause;
+	register_t	vadr;
+	register_t	pc;
+	register_t	ra;
+	register_t	sp;
+	register_t	code;
 };
 
 #define	trapdebug_enter(x, cd) {	\
@@ -117,7 +117,7 @@ void MipsUserGenException(void);
 void MipsUserIntr(void);
 void MipsUserTLBInvalidException(void);
 
-u_int trap(struct trapframe *);
+register_t trap(struct trapframe *);
 
 #ifndef LOCORE /* XXX */
 int check_address(void *);

Modified: user/jmallett/octeon/sys/mips/mips/trap.c
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/trap.c	Sat Feb 27 05:45:32 2010	(r204398)
+++ user/jmallett/octeon/sys/mips/mips/trap.c	Sat Feb 27 05:46:40 2010	(r204399)
@@ -274,7 +274,7 @@ extern char *syscallnames[];
  * In the case of a kernel trap, we return the pc where to resume if
  * p->p_addr->u_pcb.pcb_onfault is set, otherwise, return old pc.
  */
-u_int
+register_t
 trap(struct trapframe *trapframe)
 {
 	int type, usermode;
@@ -1001,11 +1001,11 @@ trapDump(char *msg)
 		if (trp->cause == 0)
 			break;
 
-		printf("%s: ADR %x PC %x CR %x SR %x\n",
+		printf("%s: ADR %jx PC %jx CR %jx SR %jx\n",
 		    trap_type[(trp->cause & CR_EXC_CODE) >> CR_EXC_CODE_SHIFT],
-		    trp->vadr, trp->pc, trp->cause, trp->status);
+		    (intmax_t)trp->vadr, (intmax_t)trp->pc, (intmax_t)trp->cause, (intmax_t)trp->status);
 
-		printf("   RA %x SP %x code %d\n", trp->ra, trp->sp, trp->code);
+		printf("   RA %jx SP %jx code %d\n", (intmax_t)trp->ra, (intmax_t)trp->sp, (int)trp->code);
 	}
 	restoreintr(s);
 }

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