Date: Sat, 5 Dec 2015 08:34:51 +0000 (UTC) From: Andrew Rybchenko <arybchik@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r291849 - head/sys/dev/sfxge/common Message-ID: <201512050834.tB58YpLa085829@repo.freebsd.org>
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Author: arybchik Date: Sat Dec 5 08:34:51 2015 New Revision: 291849 URL: https://svnweb.freebsd.org/changeset/base/291849 Log: sfxge: pick up the new TLV structures The header is auto-generated from firmware sources. Sponsored by: Solarflare Communications, Inc. MFC after: 2 days Modified: head/sys/dev/sfxge/common/ef10_tlv_layout.h Modified: head/sys/dev/sfxge/common/ef10_tlv_layout.h ============================================================================== --- head/sys/dev/sfxge/common/ef10_tlv_layout.h Sat Dec 5 08:26:16 2015 (r291848) +++ head/sys/dev/sfxge/common/ef10_tlv_layout.h Sat Dec 5 08:34:51 2015 (r291849) @@ -194,7 +194,9 @@ struct tlv_port_mac { /* Static VPD. * * This is the portion of VPD which is set at manufacturing time and not - * expected to change. It is formatted as a standard PCI VPD block. + * expected to change. It is formatted as a standard PCI VPD block. There are + * global and per-pf TLVs for this, the global TLV is new for Medford and is + * used in preference to the per-pf TLV. */ #define TLV_TAG_PF_STATIC_VPD(pf) (0x00030000 + (pf)) @@ -205,11 +207,21 @@ struct tlv_pf_static_vpd { uint8_t bytes[]; }; +#define TLV_TAG_GLOBAL_STATIC_VPD (0x001f0000) + +struct tlv_global_static_vpd { + uint32_t tag; + uint32_t length; + uint8_t bytes[]; +}; + /* Dynamic VPD. * * This is the portion of VPD which may be changed (e.g. by firmware updates). - * It is formatted as a standard PCI VPD block. + * It is formatted as a standard PCI VPD block. There are global and per-pf TLVs + * for this, the global TLV is new for Medford and is used in preference to the + * per-pf TLV. */ #define TLV_TAG_PF_DYNAMIC_VPD(pf) (0x10030000 + (pf)) @@ -220,11 +232,21 @@ struct tlv_pf_dynamic_vpd { uint8_t bytes[]; }; +#define TLV_TAG_GLOBAL_DYNAMIC_VPD (0x10200000) + +struct tlv_global_dynamic_vpd { + uint32_t tag; + uint32_t length; + uint8_t bytes[]; +}; + /* "DBI" PCI config space changes. * * This is a set of edits made to the default PCI config space values before - * the device is allowed to enumerate. + * the device is allowed to enumerate. There are global and per-pf TLVs for + * this, the global TLV is new for Medford and is used in preference to the + * per-pf TLV. */ #define TLV_TAG_PF_DBI(pf) (0x00040000 + (pf)) @@ -240,6 +262,19 @@ struct tlv_pf_dbi { }; +#define TLV_TAG_GLOBAL_DBI (0x00210000) + +struct tlv_global_dbi { + uint32_t tag; + uint32_t length; + struct { + uint16_t addr; + uint16_t byte_enables; + uint32_t value; + } items[]; +}; + + /* Partition subtype codes. * * A subtype may optionally be stored for each type of partition present in @@ -289,7 +324,7 @@ struct tlv_pcie_config { int16_t max_pf_number; /**< Largest PF RID (lower PFs may be hidden) */ uint16_t pf_aper; /**< BIU aperture for PF BAR2 */ uint16_t vf_aper; /**< BIU aperture for VF BAR0 */ - uint16_t int_aper; /**< BIU aperture for PF BAR4 and VF BAR2 */ + uint16_t int_aper; /**< BIU aperture for PF BAR4 and VF BAR2 */ #define TLV_MAX_PF_DEFAULT (-1) /* Use FW default for largest PF RID */ #define TLV_APER_DEFAULT (0xFFFF) /* Use FW default for a given aperture */ }; @@ -305,13 +340,13 @@ struct tlv_per_pf_pcie_config { uint32_t tag; uint32_t length; uint8_t vfs_total; - uint8_t port_allocation; + uint8_t port_allocation; uint16_t vectors_per_pf; uint16_t vectors_per_vf; uint8_t pf_bar0_aperture; uint8_t pf_bar2_aperture; uint8_t vf_bar0_aperture; - uint8_t vf_base; + uint8_t vf_base; uint16_t supp_pagesz; uint16_t msix_vec_base; }; @@ -320,7 +355,8 @@ struct tlv_per_pf_pcie_config { /* Development ONLY. This is a single TLV tag for all the gubbins * that can be set through the MC command-line other than the PCIe * settings. This is a temporary measure. */ -#define TLV_TAG_TMP_GUBBINS (0x10090000) +#define TLV_TAG_TMP_GUBBINS (0x10090000) /* legacy symbol - do not use */ +#define TLV_TAG_TMP_GUBBINS_HUNT TLV_TAG_TMP_GUBBINS struct tlv_tmp_gubbins { uint32_t tag; @@ -393,16 +429,16 @@ struct tlv_firmware_options { }; /* Voltage settings - * + * * Intended for boards with A0 silicon where the core voltage may - * need tweaking. Most likely set once when the pass voltage is + * need tweaking. Most likely set once when the pass voltage is * determined. */ #define TLV_TAG_0V9_SETTINGS (0x000c0000) struct tlv_0v9_settings { uint32_t tag; - uint32_t length; + uint32_t length; uint16_t flags; /* Boards with high 0v9 settings may need active cooling */ #define TLV_TAG_0V9_REQUIRES_FAN (1) uint16_t target_voltage; /* In millivolts */ @@ -411,17 +447,18 @@ struct tlv_0v9_settings { uint16_t warn_low; /* In millivolts */ uint16_t warn_high; /* In millivolts */ uint16_t panic_low; /* In millivolts */ - uint16_t panic_high; /* In millivolts */ + uint16_t panic_high; /* In millivolts */ }; /* Clock configuration */ -#define TLV_TAG_CLOCK_CONFIG (0x000d0000) +#define TLV_TAG_CLOCK_CONFIG (0x000d0000) /* legacy symbol - do not use */ +#define TLV_TAG_CLOCK_CONFIG_HUNT TLV_TAG_CLOCK_CONFIG struct tlv_clock_config { uint32_t tag; - uint32_t length; + uint32_t length; uint16_t clk_sys; /* MHz */ uint16_t clk_dpcpu; /* MHz */ uint16_t clk_icore; /* MHz */ @@ -460,7 +497,8 @@ struct tlv_global_mac { uint16_t reserved2; }; -#define TLV_TAG_ATB_0V9_TARGET (0x000f0000) +#define TLV_TAG_ATB_0V9_TARGET (0x000f0000) /* legacy symbol - do not use */ +#define TLV_TAG_ATB_0V9_TARGET_HUNT TLV_TAG_ATB_0V9_TARGET /* The target value for the 0v9 power rail measured on-chip at the * analogue test bus */ @@ -485,7 +523,7 @@ struct tlv_pcie_config_r2 { uint16_t visible_pfs; /**< Bitmap of visible PFs */ uint16_t pf_aper; /**< BIU aperture for PF BAR2 */ uint16_t vf_aper; /**< BIU aperture for VF BAR0 */ - uint16_t int_aper; /**< BIU aperture for PF BAR4 and VF BAR2 */ + uint16_t int_aper; /**< BIU aperture for PF BAR4 and VF BAR2 */ }; /* Dynamic port mode.
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