Date: Fri, 1 Mar 2013 17:57:12 +0900 From: "Daisuke Aoyama" <aoyama@peach.ne.jp> To: "Oleksandr Tymoshenko" <gonzo@bluezbox.com> Cc: freebsd-arm@freebsd.org Subject: Re: FreeBSD/armv6z/clang on Raspberry Pi 512MB (with U-Boot + ubldr) Message-ID: <2D2EAE5B346840A49A5D99A9BFD1DA1D@ad.peach.ne.jp> In-Reply-To: <512FD3E8.4000307@bluezbox.com> References: <B5F827FF91C94FF2AFEE00194A2BB2C5@ad.peach.ne.jp> <B508111FCE534B2CBA61F4D1EC1078D3@ad.peach.ne.jp> <D3ABE3919EA74D668DB060952B5CD8C0@ad.peach.ne.jp> <2659960079254C38ACD2F1DCBB7A1A19@ad.peach.ne.jp> <E48DEAF481F74C69A1BC7A01F2B8E74A@ad.peach.ne.jp> <D867259F89CF44409C2359527D0263D4@ad.peach.ne.jp> <512FD3E8.4000307@bluezbox.com>
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> I'd like to thank you again for your outstanding work. > I've just committed three patches based on your code: > > - Platform DMA support for SDHCI > - DMA engine driver > - DMA support for BCM2835 SDHCI driver Thank you. I checked the code and found some bug. I don't check why bus_dma and bus_space is slow. But using generic code is good. ---------------------------------------------------------------------- o INFO_WAIT_RESP is cleared when reset. o dreq is overwritten by next call. o should reset DMA when error. quick fix is like this: --- bcm2835_dma.c (revision 247518) +++ bcm2835_dma.c (working copy) @@ -199,6 +199,7 @@ /* Reset control block */ cb = sc->sc_dma_ch[ch].cb; bzero(cb, sizeof(cb)); + cb->info = INFO_WAIT_RESP; /* XXX */ } static int @@ -409,8 +410,10 @@ return (-1); info = sc->sc_dma_ch[ch].cb->info; - info &= ~INFO_PERMAP_MASK; - info |= (dreq << INFO_PERMAP_SHIFT) & INFO_PERMAP_MASK; + if (dreq) { + info &= ~INFO_PERMAP_MASK; + info |= (dreq << INFO_PERMAP_SHIFT) & INFO_PERMAP_MASK; + } if (dreq) info |= INFO_S_DREQ; @@ -459,8 +462,10 @@ return (-1); info = sc->sc_dma_ch[ch].cb->info; - info &= ~INFO_PERMAP_MASK; - info |= (dreq << INFO_PERMAP_SHIFT) & INFO_PERMAP_MASK; + if (dreq) { + info &= ~INFO_PERMAP_MASK; + info |= (dreq << INFO_PERMAP_SHIFT) & INFO_PERMAP_MASK; + } if (dreq) info |= INFO_D_DREQ; @@ -615,6 +693,7 @@ debug & DEBUG_ERROR_MASK, ch->ch); bus_write_4(sc->sc_mem, BCM_DMA_DEBUG(ch->ch), debug & DEBUG_ERROR_MASK); + bcm_dma_reset(sc->sc_dev, ch->ch); } if (cs & CS_INT) { ---------------------------------------------------------------------- -- Daisuke Aoyama
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