Date: Fri, 30 Jul 1999 11:28:35 -0400 (EDT) From: "Brian F. Feldman" <green@FreeBSD.org> To: Mike Smith <mike@smith.net.au> Cc: Stephen Hocking-Senior Programmer PGS Tensor Perth <shocking@prth.pgs.com>, current@FreeBSD.org Subject: Re: MTRR stuff Message-ID: <Pine.BSF.4.10.9907301126470.442-100000@janus.syracuse.net> In-Reply-To: <199907300934.CAA02191@dingo.cdrom.com>
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On Fri, 30 Jul 1999, Mike Smith wrote:
> > For some video cards (to wit, the voodoo stuff), the MTRRs should be set up as
> > follows
> >
> > write-combining
> > +----------------------------------------------------------+
> > +-------+
> > uncacheable
> >
> > i.e. the two regions have the same starting area, but the small chunk for the
> > registers should be uncacheable. When I try to do this using memconf on my
> > K6-2, it spits the dummy. Is there a work around for this?
>
> The i686 MTRR implementation, at least, doesn't allow UC to overlap WC;
> only Write-back and uncached are allowed to overlap. I don't know what
> the K6's limitations are; you should talk to Brian Feldman about that.
As long as a range isn't exactly the same (base, len being the same), it
allows the change. The question is how does it fail? I let the hardware
decide what to actually do with the registers, but I write them, so...
I need to know where the problem is.
>
> --
> \\ The mind's the standard \\ Mike Smith
> \\ of the man. \\ msmith@freebsd.org
> \\ -- Joseph Merrick \\ msmith@cdrom.com
>
>
>
>
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