Date: Wed, 4 Jun 2014 18:19:10 +0000 (UTC) From: Attilio Rao <attilio@FreeBSD.org> To: src-committers@freebsd.org, svn-src-user@freebsd.org Subject: svn commit: r267073 - in user/attilio/rm_vmobj_cache: lib/libpmc sbin/geom/class/label sys/dev/hwpmc sys/dev/usb/wlan sys/dev/virtio/network sys/fs/tmpfs sys/sys usr.bin/netstat usr.bin/yes Message-ID: <201406041819.s54IJAvk039141@svn.freebsd.org>
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Author: attilio Date: Wed Jun 4 18:19:10 2014 New Revision: 267073 URL: http://svnweb.freebsd.org/changeset/base/267073 Log: Merge from head. Modified: user/attilio/rm_vmobj_cache/lib/libpmc/libpmc.c user/attilio/rm_vmobj_cache/sbin/geom/class/label/glabel.8 user/attilio/rm_vmobj_cache/sys/dev/hwpmc/hwpmc_core.c user/attilio/rm_vmobj_cache/sys/dev/hwpmc/hwpmc_intel.c user/attilio/rm_vmobj_cache/sys/dev/usb/wlan/if_rsu.c user/attilio/rm_vmobj_cache/sys/dev/virtio/network/if_vtnet.c user/attilio/rm_vmobj_cache/sys/fs/tmpfs/tmpfs_subr.c user/attilio/rm_vmobj_cache/sys/sys/pmc.h user/attilio/rm_vmobj_cache/usr.bin/netstat/netstat.1 user/attilio/rm_vmobj_cache/usr.bin/yes/yes.1 Directory Properties: user/attilio/rm_vmobj_cache/ (props changed) user/attilio/rm_vmobj_cache/sbin/ (props changed) user/attilio/rm_vmobj_cache/sys/ (props changed) Modified: user/attilio/rm_vmobj_cache/lib/libpmc/libpmc.c ============================================================================== --- user/attilio/rm_vmobj_cache/lib/libpmc/libpmc.c Wed Jun 4 18:16:46 2014 (r267072) +++ user/attilio/rm_vmobj_cache/lib/libpmc/libpmc.c Wed Jun 4 18:19:10 2014 (r267073) @@ -190,6 +190,11 @@ static const struct pmc_event_descr core __PMC_EV_ALIAS_COREI7() }; +static const struct pmc_event_descr nehalem_ex_event_table[] = +{ + __PMC_EV_ALIAS_COREI7() +}; + static const struct pmc_event_descr haswell_event_table[] = { __PMC_EV_ALIAS_HASWELL() @@ -220,6 +225,11 @@ static const struct pmc_event_descr west __PMC_EV_ALIAS_WESTMERE() }; +static const struct pmc_event_descr westmere_ex_event_table[] = +{ + __PMC_EV_ALIAS_WESTMERE() +}; + static const struct pmc_event_descr corei7uc_event_table[] = { __PMC_EV_ALIAS_COREI7UC() @@ -255,12 +265,14 @@ PMC_MDEP_TABLE(atom_silvermont, IAP, PMC PMC_MDEP_TABLE(core, IAP, PMC_CLASS_SOFT, PMC_CLASS_TSC); PMC_MDEP_TABLE(core2, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); PMC_MDEP_TABLE(corei7, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); +PMC_MDEP_TABLE(nehalem_ex, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); PMC_MDEP_TABLE(haswell, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); PMC_MDEP_TABLE(ivybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); PMC_MDEP_TABLE(ivybridge_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); PMC_MDEP_TABLE(sandybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); PMC_MDEP_TABLE(sandybridge_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); PMC_MDEP_TABLE(westmere, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); +PMC_MDEP_TABLE(westmere_ex, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); PMC_MDEP_TABLE(k7, K7, PMC_CLASS_SOFT, PMC_CLASS_TSC); PMC_MDEP_TABLE(k8, K8, PMC_CLASS_SOFT, PMC_CLASS_TSC); PMC_MDEP_TABLE(p4, P4, PMC_CLASS_SOFT, PMC_CLASS_TSC); @@ -298,12 +310,14 @@ PMC_CLASS_TABLE_DESC(atom_silvermont, IA PMC_CLASS_TABLE_DESC(core, IAP, core, iap); PMC_CLASS_TABLE_DESC(core2, IAP, core2, iap); PMC_CLASS_TABLE_DESC(corei7, IAP, corei7, iap); +PMC_CLASS_TABLE_DESC(nehalem_ex, IAP, nehalem_ex, iap); PMC_CLASS_TABLE_DESC(haswell, IAP, haswell, iap); PMC_CLASS_TABLE_DESC(ivybridge, IAP, ivybridge, iap); PMC_CLASS_TABLE_DESC(ivybridge_xeon, IAP, ivybridge_xeon, iap); PMC_CLASS_TABLE_DESC(sandybridge, IAP, sandybridge, iap); PMC_CLASS_TABLE_DESC(sandybridge_xeon, IAP, sandybridge_xeon, iap); PMC_CLASS_TABLE_DESC(westmere, IAP, westmere, iap); +PMC_CLASS_TABLE_DESC(westmere_ex, IAP, westmere_ex, iap); PMC_CLASS_TABLE_DESC(ucf, UCF, ucf, ucf); PMC_CLASS_TABLE_DESC(corei7uc, UCP, corei7uc, ucp); PMC_CLASS_TABLE_DESC(haswelluc, UCP, haswelluc, ucp); @@ -608,6 +622,8 @@ static struct pmc_event_alias core2_alia #define atom_silvermont_aliases_without_iaf core2_aliases_without_iaf #define corei7_aliases core2_aliases #define corei7_aliases_without_iaf core2_aliases_without_iaf +#define nehalem_ex_aliases core2_aliases +#define nehalem_ex_aliases_without_iaf core2_aliases_without_iaf #define haswell_aliases core2_aliases #define haswell_aliases_without_iaf core2_aliases_without_iaf #define ivybridge_aliases core2_aliases @@ -620,6 +636,8 @@ static struct pmc_event_alias core2_alia #define sandybridge_xeon_aliases_without_iaf core2_aliases_without_iaf #define westmere_aliases core2_aliases #define westmere_aliases_without_iaf core2_aliases_without_iaf +#define westmere_ex_aliases core2_aliases +#define westmere_ex_aliases_without_iaf core2_aliases_without_iaf #define IAF_KW_OS "os" #define IAF_KW_USR "usr" @@ -863,7 +881,9 @@ iap_allocate_pmc(enum pmc_event pe, char } else return (-1); } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_COREI7 || - cpu_info.pm_cputype == PMC_CPU_INTEL_WESTMERE) { + cpu_info.pm_cputype == PMC_CPU_INTEL_WESTMERE || + cpu_info.pm_cputype == PMC_CPU_INTEL_NEHALEM_EX || + cpu_info.pm_cputype == PMC_CPU_INTEL_WESTMERE_EX) { if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) { n = pmc_parse_mask(iap_rsp_mask_i7_wm, p, &rsp); } else @@ -2760,6 +2780,10 @@ pmc_event_names_of_class(enum pmc_class ev = corei7_event_table; count = PMC_EVENT_TABLE_SIZE(corei7); break; + case PMC_CPU_INTEL_NEHALEM_EX: + ev = nehalem_ex_event_table; + count = PMC_EVENT_TABLE_SIZE(nehalem_ex); + break; case PMC_CPU_INTEL_HASWELL: ev = haswell_event_table; count = PMC_EVENT_TABLE_SIZE(haswell); @@ -2784,6 +2808,10 @@ pmc_event_names_of_class(enum pmc_class ev = westmere_event_table; count = PMC_EVENT_TABLE_SIZE(westmere); break; + case PMC_CPU_INTEL_WESTMERE_EX: + ev = westmere_ex_event_table; + count = PMC_EVENT_TABLE_SIZE(westmere_ex); + break; } break; case PMC_CLASS_UCF: @@ -3079,6 +3107,9 @@ pmc_init(void) pmc_class_table[n++] = &corei7uc_class_table_descr; PMC_MDEP_INIT_INTEL_V2(corei7); break; + case PMC_CPU_INTEL_NEHALEM_EX: + PMC_MDEP_INIT_INTEL_V2(nehalem_ex); + break; case PMC_CPU_INTEL_HASWELL: pmc_class_table[n++] = &ucf_class_table_descr; pmc_class_table[n++] = &haswelluc_class_table_descr; @@ -3103,6 +3134,9 @@ pmc_init(void) pmc_class_table[n++] = &westmereuc_class_table_descr; PMC_MDEP_INIT_INTEL_V2(westmere); break; + case PMC_CPU_INTEL_WESTMERE_EX: + PMC_MDEP_INIT_INTEL_V2(westmere_ex); + break; case PMC_CPU_INTEL_PIV: PMC_MDEP_INIT(p4); pmc_class_table[n] = &p4_class_table_descr; @@ -3237,6 +3271,11 @@ _pmc_name_of_event(enum pmc_event pe, en ev = corei7_event_table; evfence = corei7_event_table + PMC_EVENT_TABLE_SIZE(corei7); break; + case PMC_CPU_INTEL_NEHALEM_EX: + ev = nehalem_ex_event_table; + evfence = nehalem_ex_event_table + + PMC_EVENT_TABLE_SIZE(nehalem_ex); + break; case PMC_CPU_INTEL_HASWELL: ev = haswell_event_table; evfence = haswell_event_table + PMC_EVENT_TABLE_SIZE(haswell); @@ -3261,6 +3300,11 @@ _pmc_name_of_event(enum pmc_event pe, en ev = westmere_event_table; evfence = westmere_event_table + PMC_EVENT_TABLE_SIZE(westmere); break; + case PMC_CPU_INTEL_WESTMERE_EX: + ev = westmere_ex_event_table; + evfence = westmere_ex_event_table + + PMC_EVENT_TABLE_SIZE(westmere_ex); + break; default: /* Unknown CPU type. */ break; } Modified: user/attilio/rm_vmobj_cache/sbin/geom/class/label/glabel.8 ============================================================================== --- user/attilio/rm_vmobj_cache/sbin/geom/class/label/glabel.8 Wed Jun 4 18:16:46 2014 (r267072) +++ user/attilio/rm_vmobj_cache/sbin/geom/class/label/glabel.8 Wed Jun 4 18:19:10 2014 (r267073) @@ -223,6 +223,19 @@ This can be set to a number between 0 an If set to 0 minimal debug information is printed, and if set to 2 the maximum amount of debug information is printed. .El +.Bl -tag -width indent +.It Va kern.geom.label.*.enable : No 1 +Most +.Nm LABEL +providers implement a +.Xr sysctl 8 +flag and a tunable variable named in the above format. This flag +controls if the label provider will be active, tasting devices +and creating label nodes in the +.Xr devfs 5 +tree. It is sometimes desirable to disable certain label types if +they conflict with other classes in complex GEOM topologies. +.Bl .Sh EXIT STATUS Exit status is 0 on success, and 1 if the command fails. .Sh EXAMPLES Modified: user/attilio/rm_vmobj_cache/sys/dev/hwpmc/hwpmc_core.c ============================================================================== --- user/attilio/rm_vmobj_cache/sys/dev/hwpmc/hwpmc_core.c Wed Jun 4 18:16:46 2014 (r267072) +++ user/attilio/rm_vmobj_cache/sys/dev/hwpmc/hwpmc_core.c Wed Jun 4 18:19:10 2014 (r267073) @@ -2021,6 +2021,7 @@ iap_allocate_pmc(int cpu, int ri, struct switch (core_cputype) { case PMC_CPU_INTEL_COREI7: + case PMC_CPU_INTEL_NEHALEM_EX: if (iap_event_corei7_ok_on_counter(ev, ri) == 0) return (EINVAL); break; @@ -2033,6 +2034,7 @@ iap_allocate_pmc(int cpu, int ri, struct return (EINVAL); break; case PMC_CPU_INTEL_WESTMERE: + case PMC_CPU_INTEL_WESTMERE_EX: if (iap_event_westmere_ok_on_counter(ev, ri) == 0) return (EINVAL); break; @@ -2186,7 +2188,9 @@ iap_allocate_pmc(int cpu, int ri, struct ev == PMC_EV_IAP_EVENT_BBH_01H) return (EINVAL); if ((core_cputype == PMC_CPU_INTEL_COREI7 || - core_cputype == PMC_CPU_INTEL_WESTMERE) && + core_cputype == PMC_CPU_INTEL_WESTMERE || + core_cputype == PMC_CPU_INTEL_NEHALEM_EX || + core_cputype == PMC_CPU_INTEL_WESTMERE_EX) && a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK_I7WM) return (EINVAL); else if ((core_cputype == PMC_CPU_INTEL_SANDYBRIDGE || Modified: user/attilio/rm_vmobj_cache/sys/dev/hwpmc/hwpmc_intel.c ============================================================================== --- user/attilio/rm_vmobj_cache/sys/dev/hwpmc/hwpmc_intel.c Wed Jun 4 18:16:46 2014 (r267072) +++ user/attilio/rm_vmobj_cache/sys/dev/hwpmc/hwpmc_intel.c Wed Jun 4 18:19:10 2014 (r267073) @@ -147,15 +147,22 @@ pmc_intel_initialize(void) * Per Intel document 253669-032 9/2009, * pages A-2 and A-57 */ - case 0x2E: cputype = PMC_CPU_INTEL_COREI7; nclasses = 5; break; + case 0x2E: + cputype = PMC_CPU_INTEL_NEHALEM_EX; + nclasses = 3; + break; case 0x25: /* Per Intel document 253669-033US 12/2009. */ case 0x2C: /* Per Intel document 253669-033US 12/2009. */ cputype = PMC_CPU_INTEL_WESTMERE; nclasses = 5; break; + case 0x2F: /* Westmere-EX, seen in wild */ + cputype = PMC_CPU_INTEL_WESTMERE_EX; + nclasses = 3; + break; case 0x2A: /* Per Intel document 253669-039US 05/2011. */ cputype = PMC_CPU_INTEL_SANDYBRIDGE; nclasses = 5; @@ -218,9 +225,11 @@ pmc_intel_initialize(void) case PMC_CPU_INTEL_CORE2: case PMC_CPU_INTEL_CORE2EXTREME: case PMC_CPU_INTEL_COREI7: + case PMC_CPU_INTEL_NEHALEM_EX: case PMC_CPU_INTEL_IVYBRIDGE: case PMC_CPU_INTEL_SANDYBRIDGE: case PMC_CPU_INTEL_WESTMERE: + case PMC_CPU_INTEL_WESTMERE_EX: case PMC_CPU_INTEL_SANDYBRIDGE_XEON: case PMC_CPU_INTEL_IVYBRIDGE_XEON: case PMC_CPU_INTEL_HASWELL: @@ -307,10 +316,12 @@ pmc_intel_finalize(struct pmc_mdep *md) case PMC_CPU_INTEL_CORE2: case PMC_CPU_INTEL_CORE2EXTREME: case PMC_CPU_INTEL_COREI7: + case PMC_CPU_INTEL_NEHALEM_EX: case PMC_CPU_INTEL_HASWELL: case PMC_CPU_INTEL_IVYBRIDGE: case PMC_CPU_INTEL_SANDYBRIDGE: case PMC_CPU_INTEL_WESTMERE: + case PMC_CPU_INTEL_WESTMERE_EX: case PMC_CPU_INTEL_SANDYBRIDGE_XEON: case PMC_CPU_INTEL_IVYBRIDGE_XEON: pmc_core_finalize(md); Modified: user/attilio/rm_vmobj_cache/sys/dev/usb/wlan/if_rsu.c ============================================================================== --- user/attilio/rm_vmobj_cache/sys/dev/usb/wlan/if_rsu.c Wed Jun 4 18:16:46 2014 (r267072) +++ user/attilio/rm_vmobj_cache/sys/dev/usb/wlan/if_rsu.c Wed Jun 4 18:19:10 2014 (r267073) @@ -1057,7 +1057,8 @@ rsu_join_bss(struct rsu_softc *sc, struc struct ndis_wlan_bssid_ex *bss; struct ndis_802_11_fixed_ies *fixed; struct r92s_fw_cmd_auth auth; - uint8_t buf[sizeof(*bss) + 128], *frm; + uint8_t buf[sizeof(*bss) + 128] __aligned(4); + uint8_t *frm; uint8_t opmode; int error; @@ -1071,7 +1072,7 @@ rsu_join_bss(struct rsu_softc *sc, struc memset(&auth, 0, sizeof(auth)); if (vap->iv_flags & IEEE80211_F_WPA) { auth.mode = R92S_AUTHMODE_WPA; - auth.dot1x = ni->ni_authmode == IEEE80211_AUTH_8021X; + auth.dot1x = (ni->ni_authmode == IEEE80211_AUTH_8021X); } else auth.mode = R92S_AUTHMODE_OPEN; DPRINTF("setting auth mode to %d\n", auth.mode); @@ -1192,6 +1193,7 @@ rsu_event_join_bss(struct rsu_softc *sc, struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); struct ieee80211_node *ni = vap->iv_bss; struct r92s_event_join_bss *rsp; + uint32_t tmp; int res; if (__predict_false(len < sizeof(*rsp))) @@ -1206,9 +1208,14 @@ rsu_event_join_bss(struct rsu_softc *sc, RSU_LOCK(sc); return; } + tmp = le32toh(rsp->associd); + if (tmp >= vap->iv_max_aid) { + DPRINTF("Assoc ID overflow\n"); + tmp = 1; + } DPRINTF("associated with %s associd=%d\n", - ether_sprintf(rsp->bss.macaddr), le32toh(rsp->associd)); - ni->ni_associd = le32toh(rsp->associd) | 0xc000; + ether_sprintf(rsp->bss.macaddr), tmp); + ni->ni_associd = tmp | 0xc000; RSU_UNLOCK(sc); ieee80211_new_state(vap, IEEE80211_S_RUN, IEEE80211_FC0_SUBTYPE_ASSOC_RESP); Modified: user/attilio/rm_vmobj_cache/sys/dev/virtio/network/if_vtnet.c ============================================================================== --- user/attilio/rm_vmobj_cache/sys/dev/virtio/network/if_vtnet.c Wed Jun 4 18:16:46 2014 (r267072) +++ user/attilio/rm_vmobj_cache/sys/dev/virtio/network/if_vtnet.c Wed Jun 4 18:19:10 2014 (r267073) @@ -2262,7 +2262,6 @@ vtnet_txq_mq_start_locked(struct vtnet_t while ((m = drbr_peek(ifp, br)) != NULL) { if (virtqueue_full(vq)) { drbr_putback(ifp, br, m); - error = ENOBUFS; break; } @@ -2285,7 +2284,7 @@ vtnet_txq_mq_start_locked(struct vtnet_t txq->vtntx_watchdog = VTNET_TX_TIMEOUT; } - return (error); + return (0); } static int Modified: user/attilio/rm_vmobj_cache/sys/fs/tmpfs/tmpfs_subr.c ============================================================================== --- user/attilio/rm_vmobj_cache/sys/fs/tmpfs/tmpfs_subr.c Wed Jun 4 18:16:46 2014 (r267072) +++ user/attilio/rm_vmobj_cache/sys/fs/tmpfs/tmpfs_subr.c Wed Jun 4 18:19:10 2014 (r267073) @@ -595,6 +595,8 @@ loop1: default: panic("tmpfs_alloc_vp: type %p %d", node, (int)node->tn_type); } + if (vp->v_type != VFIFO) + VN_LOCK_ASHARE(vp); error = insmntque1(vp, mp, tmpfs_insmntque_dtr, NULL); if (error) Modified: user/attilio/rm_vmobj_cache/sys/sys/pmc.h ============================================================================== --- user/attilio/rm_vmobj_cache/sys/sys/pmc.h Wed Jun 4 18:16:46 2014 (r267072) +++ user/attilio/rm_vmobj_cache/sys/sys/pmc.h Wed Jun 4 18:19:10 2014 (r267073) @@ -92,6 +92,8 @@ __PMC_CPU(INTEL_IVYBRIDGE_XEON, 0x90, "Intel Ivy Bridge Xeon") \ __PMC_CPU(INTEL_HASWELL, 0x91, "Intel Haswell") \ __PMC_CPU(INTEL_ATOM_SILVERMONT, 0x92, "Intel Atom Silvermont") \ + __PMC_CPU(INTEL_NEHALEM_EX, 0x93, "Intel Nehalem Xeon 7500") \ + __PMC_CPU(INTEL_WESTMERE_EX, 0x94, "Intel Westmere Xeon E7") \ __PMC_CPU(INTEL_XSCALE, 0x100, "Intel XScale") \ __PMC_CPU(MIPS_24K, 0x200, "MIPS 24K") \ __PMC_CPU(MIPS_OCTEON, 0x201, "Cavium Octeon") \ Modified: user/attilio/rm_vmobj_cache/usr.bin/netstat/netstat.1 ============================================================================== --- user/attilio/rm_vmobj_cache/usr.bin/netstat/netstat.1 Wed Jun 4 18:16:46 2014 (r267072) +++ user/attilio/rm_vmobj_cache/usr.bin/netstat/netstat.1 Wed Jun 4 18:19:10 2014 (r267073) @@ -28,7 +28,7 @@ .\" @(#)netstat.1 8.8 (Berkeley) 4/18/94 .\" $FreeBSD$ .\" -.Dd July 4, 2014 +.Dd June 4, 2014 .Dt NETSTAT 1 .Os .Sh NAME Modified: user/attilio/rm_vmobj_cache/usr.bin/yes/yes.1 ============================================================================== --- user/attilio/rm_vmobj_cache/usr.bin/yes/yes.1 Wed Jun 4 18:16:46 2014 (r267072) +++ user/attilio/rm_vmobj_cache/usr.bin/yes/yes.1 Wed Jun 4 18:19:10 2014 (r267073) @@ -28,7 +28,7 @@ .\" @(#)yes.1 8.1 (Berkeley) 6/6/93 .\" $FreeBSD$ .\" -.Dd June 6, 1993 +.Dd June 4, 2014 .Dt YES 1 .Os .Sh NAME @@ -45,6 +45,9 @@ utility outputs or, by default, .Dq y , forever. +.Sh SEE ALSO +.Xr jot 1 , +.Xr seq 1 . .Sh HISTORY The .Nm
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