Date: Thu, 25 Nov 2021 16:21:53 GMT From: Alexander Motin <mav@FreeBSD.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org Subject: git: 52d973f52c07 - main - libpmc: Update some x86 event definitions. Message-ID: <202111251621.1APGLrGR039827@gitrepo.freebsd.org>
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The branch main has been updated by mav: URL: https://cgit.FreeBSD.org/src/commit/?id=52d973f52c07b94909a6487be373c269988dc151 commit 52d973f52c07b94909a6487be373c269988dc151 Author: Alexander Motin <mav@FreeBSD.org> AuthorDate: 2021-11-25 16:19:26 +0000 Commit: Alexander Motin <mav@FreeBSD.org> CommitDate: 2021-11-25 16:19:26 +0000 libpmc: Update some x86 event definitions. MFC after: 1 month --- lib/libpmc/pmu-events/arch/x86/amdzen1/branch.json | 5 + lib/libpmc/pmu-events/arch/x86/amdzen1/cache.json | 83 +- lib/libpmc/pmu-events/arch/x86/amdzen1/core.json | 14 +- .../pmu-events/arch/x86/amdzen1/data-fabric.json | 2766 +--------- .../arch/x86/amdzen1/floating-point.json | 42 +- .../pmu-events/arch/x86/amdzen1/l3cache.json | 5411 ------------------- lib/libpmc/pmu-events/arch/x86/amdzen1/memory.json | 42 +- lib/libpmc/pmu-events/arch/x86/amdzen1/other.json | 12 +- .../pmu-events/arch/x86/amdzen1/recommended.json | 178 + lib/libpmc/pmu-events/arch/x86/amdzen2/branch.json | 8 +- lib/libpmc/pmu-events/arch/x86/amdzen2/cache.json | 79 +- lib/libpmc/pmu-events/arch/x86/amdzen2/core.json | 14 +- .../pmu-events/arch/x86/amdzen2/data-fabric.json | 98 + .../arch/x86/amdzen2/floating-point.json | 42 +- lib/libpmc/pmu-events/arch/x86/amdzen2/memory.json | 86 +- lib/libpmc/pmu-events/arch/x86/amdzen2/other.json | 20 +- .../pmu-events/arch/x86/amdzen2/recommended.json | 178 + .../pmu-events/arch/x86/broadwell/bdw-metrics.json | 2 +- .../arch/x86/broadwellde/bdwde-metrics.json | 2 +- .../arch/x86/broadwellx/bdx-metrics.json | 2 +- .../pmu-events/arch/x86/cascadelakex/cache.json | 5468 ++++++++++---------- .../arch/x86/cascadelakex/clx-metrics.json | 322 +- .../arch/x86/cascadelakex/floating-point.json | 48 +- .../pmu-events/arch/x86/cascadelakex/frontend.json | 566 +- .../pmu-events/arch/x86/cascadelakex/memory.json | 5452 +++++++++---------- .../pmu-events/arch/x86/cascadelakex/other.json | 4160 +++++++-------- .../pmu-events/arch/x86/cascadelakex/pipeline.json | 1062 ++-- .../arch/x86/cascadelakex/uncore-memory.json | 9 - .../arch/x86/cascadelakex/uncore-other.json | 180 +- .../arch/x86/cascadelakex/virtual-memory.json | 256 +- .../pmu-events/arch/x86/elkhartlake/cache.json | 226 + .../arch/x86/elkhartlake/ehl-metrics.json | 57 + .../arch/x86/elkhartlake/floating-point.json | 24 + .../pmu-events/arch/x86/elkhartlake/frontend.json | 93 + .../pmu-events/arch/x86/elkhartlake/memory.json | 86 + .../pmu-events/arch/x86/elkhartlake/other.json | 424 ++ .../pmu-events/arch/x86/elkhartlake/pipeline.json | 278 + .../arch/x86/elkhartlake/virtual-memory.json | 273 + .../pmu-events/arch/x86/haswell/hsw-metrics.json | 2 +- .../pmu-events/arch/x86/haswellx/hsx-metrics.json | 2 +- lib/libpmc/pmu-events/arch/x86/icelake/cache.json | 724 +-- .../arch/x86/icelake/floating-point.json | 101 +- .../pmu-events/arch/x86/icelake/frontend.json | 610 ++- .../pmu-events/arch/x86/icelake/icl-metrics.json | 273 + lib/libpmc/pmu-events/arch/x86/icelake/memory.json | 654 ++- lib/libpmc/pmu-events/arch/x86/icelake/other.json | 1089 +++- .../pmu-events/arch/x86/icelake/pipeline.json | 1169 +++-- .../arch/x86/icelake/virtual-memory.json | 251 +- lib/libpmc/pmu-events/arch/x86/icelakex/cache.json | 706 +++ .../arch/x86/icelakex/floating-point.json | 95 + .../pmu-events/arch/x86/icelakex/frontend.json | 469 ++ .../pmu-events/arch/x86/icelakex/icx-metrics.json | 315 ++ .../pmu-events/arch/x86/icelakex/memory.json | 291 ++ lib/libpmc/pmu-events/arch/x86/icelakex/other.json | 181 + .../pmu-events/arch/x86/icelakex/pipeline.json | 972 ++++ .../arch/x86/icelakex/uncore-memory.json | 333 ++ .../pmu-events/arch/x86/icelakex/uncore-other.json | 2476 +++++++++ .../pmu-events/arch/x86/icelakex/uncore-power.json | 10 + .../arch/x86/icelakex/virtual-memory.json | 245 + .../pmu-events/arch/x86/ivybridge/ivb-metrics.json | 2 +- .../pmu-events/arch/x86/ivytown/ivt-metrics.json | 2 +- .../pmu-events/arch/x86/jaketown/jkt-metrics.json | 2 +- lib/libpmc/pmu-events/arch/x86/mapfile.csv | 6 + .../arch/x86/sandybridge/snb-metrics.json | 2 +- lib/libpmc/pmu-events/arch/x86/skylake/cache.json | 4100 ++++++++------- .../arch/x86/skylake/floating-point.json | 76 +- .../pmu-events/arch/x86/skylake/frontend.json | 644 +-- lib/libpmc/pmu-events/arch/x86/skylake/memory.json | 2279 ++++---- lib/libpmc/pmu-events/arch/x86/skylake/other.json | 60 +- .../pmu-events/arch/x86/skylake/pipeline.json | 1266 ++--- .../pmu-events/arch/x86/skylake/skl-metrics.json | 273 +- .../arch/x86/skylake/virtual-memory.json | 374 +- lib/libpmc/pmu-events/arch/x86/skylakex/cache.json | 2282 ++++---- .../arch/x86/skylakex/floating-point.json | 88 +- .../pmu-events/arch/x86/skylakex/frontend.json | 732 +-- .../pmu-events/arch/x86/skylakex/memory.json | 1977 +++---- lib/libpmc/pmu-events/arch/x86/skylakex/other.json | 154 +- .../pmu-events/arch/x86/skylakex/pipeline.json | 1290 ++--- .../pmu-events/arch/x86/skylakex/skx-metrics.json | 304 +- .../arch/x86/skylakex/uncore-memory.json | 35 +- .../pmu-events/arch/x86/skylakex/uncore-other.json | 1007 +++- .../arch/x86/skylakex/virtual-memory.json | 314 +- .../pmu-events/arch/x86/tigerlake/cache.json | 595 +++ .../arch/x86/tigerlake/floating-point.json | 94 + .../pmu-events/arch/x86/tigerlake/frontend.json | 463 ++ .../pmu-events/arch/x86/tigerlake/memory.json | 295 ++ .../pmu-events/arch/x86/tigerlake/other.json | 189 + .../pmu-events/arch/x86/tigerlake/pipeline.json | 982 ++++ .../pmu-events/arch/x86/tigerlake/tgl-metrics.json | 231 + .../arch/x86/tigerlake/virtual-memory.json | 225 + 90 files changed, 32542 insertions(+), 26837 deletions(-) diff --git a/lib/libpmc/pmu-events/arch/x86/amdzen1/branch.json b/lib/libpmc/pmu-events/arch/x86/amdzen1/branch.json index a9943eeb8d6b..4ceb67a0db21 100644 --- a/lib/libpmc/pmu-events/arch/x86/amdzen1/branch.json +++ b/lib/libpmc/pmu-events/arch/x86/amdzen1/branch.json @@ -19,5 +19,10 @@ "EventName": "bp_de_redirect", "EventCode": "0x91", "BriefDescription": "Decoder Overrides Existing Branch Prediction (speculative)." + }, + { + "EventName": "bp_l1_tlb_fetch_hit", + "EventCode": "0x94", + "BriefDescription": "The number of instruction fetches that hit in the L1 ITLB." } ] diff --git a/lib/libpmc/pmu-events/arch/x86/amdzen1/cache.json b/lib/libpmc/pmu-events/arch/x86/amdzen1/cache.json index 404d4c569c01..0d46cb82bd52 100644 --- a/lib/libpmc/pmu-events/arch/x86/amdzen1/cache.json +++ b/lib/libpmc/pmu-events/arch/x86/amdzen1/cache.json @@ -38,31 +38,31 @@ "EventName": "ic_fetch_stall.ic_stall_any", "EventCode": "0x87", "BriefDescription": "Instruction Pipe Stall. IC pipe was stalled during this clock cycle for any reason (nothing valid in pipe ICM1).", - "UMask": "0x4" + "UMask": "0x04" }, { "EventName": "ic_fetch_stall.ic_stall_dq_empty", "EventCode": "0x87", "BriefDescription": "Instruction Pipe Stall. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to DQ empty.", - "UMask": "0x2" + "UMask": "0x02" }, { "EventName": "ic_fetch_stall.ic_stall_back_pressure", "EventCode": "0x87", "BriefDescription": "Instruction Pipe Stall. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to back-pressure.", - "UMask": "0x1" + "UMask": "0x01" }, { "EventName": "ic_cache_inval.l2_invalidating_probe", "EventCode": "0x8c", "BriefDescription": "IC line invalidated due to L2 invalidating probe (external or LS). The number of instruction cache lines invalidated. A non-SMC event is CMC (cross modifying code), either from the other thread of the core or another core.", - "UMask": "0x2" + "UMask": "0x02" }, { "EventName": "ic_cache_inval.fill_invalidated", "EventCode": "0x8c", "BriefDescription": "IC line invalidated due to overwriting fill response. The number of instruction cache lines invalidated. A non-SMC event is CMC (cross modifying code), either from the other thread of the core or another core.", - "UMask": "0x1" + "UMask": "0x01" }, { "EventName": "bp_tlb_rel", @@ -97,25 +97,30 @@ "EventName": "l2_request_g1.change_to_x", "EventCode": "0x60", "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Request change to writable, check L2 for current state.", - "UMask": "0x8" + "UMask": "0x08" }, { "EventName": "l2_request_g1.prefetch_l2_cmd", "EventCode": "0x60", "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.", - "UMask": "0x4" + "UMask": "0x04" }, { "EventName": "l2_request_g1.l2_hw_pf", "EventCode": "0x60", "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches accepted by L2 pipeline, hit or miss. Types of PF and L2 hit/miss broken out in a separate perfmon event.", - "UMask": "0x2" + "UMask": "0x02" }, { "EventName": "l2_request_g1.group2", "EventCode": "0x60", "BriefDescription": "Miscellaneous events covered in more detail by l2_request_g2 (PMCx061).", - "UMask": "0x1" + "UMask": "0x01" + }, + { + "EventName": "l2_request_g1.all_no_prefetch", + "EventCode": "0x60", + "UMask": "0xf9" }, { "EventName": "l2_request_g2.group1", @@ -145,31 +150,31 @@ "EventName": "l2_request_g2.ic_rd_sized_nc", "EventCode": "0x61", "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized non-cacheable.", - "UMask": "0x8" + "UMask": "0x08" }, { "EventName": "l2_request_g2.smc_inval", "EventCode": "0x61", "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Self-modifying code invalidates.", - "UMask": "0x4" + "UMask": "0x04" }, { "EventName": "l2_request_g2.bus_locks_originator", "EventCode": "0x61", "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Bus locks.", - "UMask": "0x2" + "UMask": "0x02" }, { "EventName": "l2_request_g2.bus_locks_responses", "EventCode": "0x61", "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Bus lock response.", - "UMask": "0x1" + "UMask": "0x01" }, { "EventName": "l2_latency.l2_cycles_waiting_on_fills", "EventCode": "0x62", "BriefDescription": "Total cycles spent waiting for L2 fills to complete from L3 or memory, divided by four. Event counts are for both threads. To calculate average latency, the number of fills from both threads must be used.", - "UMask": "0x1" + "UMask": "0x01" }, { "EventName": "l2_wcb_req.wcb_write", @@ -187,13 +192,13 @@ "EventName": "l2_wcb_req.zero_byte_store", "EventCode": "0x63", "BriefDescription": "LS to L2 WCB zero byte store requests. LS (Load/Store unit) to L2 WCB (Write Combining Buffer) zero byte store requests.", - "UMask": "0x4" + "UMask": "0x04" }, { "EventName": "l2_wcb_req.cl_zero", "EventCode": "0x63", "BriefDescription": "LS to L2 WCB cache line zeroing requests. LS (Load/Store unit) to L2 WCB (Write Combining Buffer) cache line zeroing requests.", - "UMask": "0x1" + "UMask": "0x01" }, { "EventName": "l2_cache_req_stat.ls_rd_blk_cs", @@ -223,31 +228,67 @@ "EventName": "l2_cache_req_stat.ls_rd_blk_c", "EventCode": "0x64", "BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data cache request miss in L2 (all types).", - "UMask": "0x8" + "UMask": "0x08" }, { "EventName": "l2_cache_req_stat.ic_fill_hit_x", "EventCode": "0x64", "BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache hit modifiable line in L2.", - "UMask": "0x4" + "UMask": "0x04" }, { "EventName": "l2_cache_req_stat.ic_fill_hit_s", "EventCode": "0x64", "BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache hit clean line in L2.", - "UMask": "0x2" + "UMask": "0x02" }, { "EventName": "l2_cache_req_stat.ic_fill_miss", "EventCode": "0x64", "BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request miss in L2.", - "UMask": "0x1" + "UMask": "0x01" + }, + { + "EventName": "l2_cache_req_stat.ic_access_in_l2", + "EventCode": "0x64", + "BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache requests in L2.", + "UMask": "0x07" + }, + { + "EventName": "l2_cache_req_stat.ic_dc_miss_in_l2", + "EventCode": "0x64", + "BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request miss in L2 and Data cache request miss in L2 (all types).", + "UMask": "0x09" + }, + { + "EventName": "l2_cache_req_stat.ic_dc_hit_in_l2", + "EventCode": "0x64", + "BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request hit in L2 and Data cache request hit in L2 (all types).", + "UMask": "0xf6" }, { "EventName": "l2_fill_pending.l2_fill_busy", "EventCode": "0x6d", "BriefDescription": "Cycles with fill pending from L2. Total cycles spent with one or more fill requests in flight from L2.", - "UMask": "0x1" + "UMask": "0x01" + }, + { + "EventName": "l2_pf_hit_l2", + "EventCode": "0x70", + "BriefDescription": "L2 prefetch hit in L2. Use l2_cache_hits_from_l2_hwpf instead.", + "UMask": "0xff" + }, + { + "EventName": "l2_pf_miss_l2_hit_l3", + "EventCode": "0x71", + "BriefDescription": "L2 prefetcher hits in L3. Counts all L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit the L3.", + "UMask": "0xff" + }, + { + "EventName": "l2_pf_miss_l2_l3", + "EventCode": "0x72", + "BriefDescription": "L2 prefetcher misses in L3. All L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches.", + "UMask": "0xff" }, { "EventName": "l3_request_g1.caching_l3_cache_accesses", diff --git a/lib/libpmc/pmu-events/arch/x86/amdzen1/core.json b/lib/libpmc/pmu-events/arch/x86/amdzen1/core.json index 7e1aa8273935..4dceeabc4a9f 100644 --- a/lib/libpmc/pmu-events/arch/x86/amdzen1/core.json +++ b/lib/libpmc/pmu-events/arch/x86/amdzen1/core.json @@ -61,28 +61,28 @@ { "EventName": "ex_ret_brn_ind_misp", "EventCode": "0xca", - "BriefDescription": "Retired Indirect Branch Instructions Mispredicted.", + "BriefDescription": "Retired Indirect Branch Instructions Mispredicted." }, { "EventName": "ex_ret_mmx_fp_instr.sse_instr", "EventCode": "0xcb", "BriefDescription": "SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX).", "PublicDescription": "The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX).", - "UMask": "0x4" + "UMask": "0x04" }, { "EventName": "ex_ret_mmx_fp_instr.mmx_instr", "EventCode": "0xcb", "BriefDescription": "MMX instructions.", "PublicDescription": "The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. MMX instructions.", - "UMask": "0x2" + "UMask": "0x02" }, { "EventName": "ex_ret_mmx_fp_instr.x87_instr", "EventCode": "0xcb", "BriefDescription": "x87 instructions.", "PublicDescription": "The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. x87 instructions.", - "UMask": "0x1" + "UMask": "0x01" }, { "EventName": "ex_ret_cond", @@ -103,19 +103,19 @@ "EventName": "ex_tagged_ibs_ops.ibs_count_rollover", "EventCode": "0x1cf", "BriefDescription": "Tagged IBS Ops. Number of times an op could not be tagged by IBS because of a previous tagged op that has not retired.", - "UMask": "0x4" + "UMask": "0x04" }, { "EventName": "ex_tagged_ibs_ops.ibs_tagged_ops_ret", "EventCode": "0x1cf", "BriefDescription": "Tagged IBS Ops. Number of Ops tagged by IBS that retired.", - "UMask": "0x2" + "UMask": "0x02" }, { "EventName": "ex_tagged_ibs_ops.ibs_tagged_ops", "EventCode": "0x1cf", "BriefDescription": "Tagged IBS Ops. Number of Ops tagged by IBS.", - "UMask": "0x1" + "UMask": "0x01" }, { "EventName": "ex_ret_fus_brnch_inst", diff --git a/lib/libpmc/pmu-events/arch/x86/amdzen1/data-fabric.json b/lib/libpmc/pmu-events/arch/x86/amdzen1/data-fabric.json index 6f138730df4f..40271df40015 100644 --- a/lib/libpmc/pmu-events/arch/x86/amdzen1/data-fabric.json +++ b/lib/libpmc/pmu-events/arch/x86/amdzen1/data-fabric.json @@ -1,2668 +1,98 @@ -[ - { - "EventName": "df_ccm_reqa.Node0.anydram", - "EventCode": "0x8B", - "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Any DRAM transaction", - "UMask": "0x0F" - }, - { - "EventName": "df_ccm_reqa.Node1.anydram", - "EventCode": "0x8B", - "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Any DRAM transaction", - "UMask": "0x2F" - }, - { - "EventName": "df_ccm_reqa.Node2.anydram", - "EventCode": "0x8B", - "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Any DRAM transaction", - "UMask": "0x4F" - }, - { - "EventName": "df_ccm_reqa.Node3.anydram", - "EventCode": "0x8B", - "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Any DRAM transaction", - "UMask": "0x6F" - }, - { - "EventName": "df_ccm_reqa.Node4.anydram", - "EventCode": "0x8B", - "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Any DRAM transaction", - "UMask": "0x8F" - }, - { - "EventName": "df_ccm_reqa.Node5.anydram", - "EventCode": "0x8B", - "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Any DRAM transaction", - "UMask": "0xAF" - }, - { - "EventName": "df_ccm_reqa.Node6.anydram", - "EventCode": "0x8B", - "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Any DRAM transaction", - "UMask": "0xCF" - }, - { - "EventName": "df_ccm_reqa.Node7.anydram", - "EventCode": "0x8B", - "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Any DRAM transaction", - "UMask": "0xEF" - }, - { - "EventName": "df_ccm_reqa.Node0.wrsizedfullzero", - "EventCode": "0x8B", - "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered WrSizedFullZero", - "UMask": "0x0E" - }, - { - "EventName": "df_ccm_reqa.Node1.wrsizedfullzero", - "EventCode": "0x8B", - "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered WrSizedFullZero", - "UMask": "0x2E" - }, - { - "EventName": "df_ccm_reqa.Node2.wrsizedfullzero", - "EventCode": "0x8B", - "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered WrSizedFullZero", - "UMask": "0x4E" - }, - { - "EventName": "df_ccm_reqa.Node3.wrsizedfullzero", - "EventCode": "0x8E", - "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered WrSizedFullZero", - "UMask": "0x6E" - }, - { - "EventName": "df_ccm_reqa.Node4.wrsizedfullzero", - "EventCode": "0x8B", - "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered WrSizedFullZero", - "UMask": "0x8E" - }, - { - "EventName": "df_ccm_reqa.Node5.wrsizedfullzero", - "EventCode": "0x8B", - "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered WrSizedFullZero", - "UMask": "0xAE" - }, - { - "EventName": "df_ccm_reqa.Node6.wrsizedfullzero", - "EventCode": "0x8B", - "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered WrSizedFullZero", - "UMask": "0xCE" - }, - { - "EventName": "df_ccm_reqa.Node7.wrsizedfullzero", - "EventCode": "0x8B", - "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered WrSizedFullZero", - "UMask": "0xEE" - }, - { - "EventName": "df_ccm_reqa.Node0.wrsizedfullnc", - "EventCode": "0x8B", - "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullnc", - "UMask": "0x0D" - }, - { - "EventName": "df_ccm_reqa.Node1.wrsizedfullnc", - "EventCode": "0x8A", - "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullnc", - "UMask": "0x2D" - }, - { - "EventName": "df_ccm_reqa.Node2.wrsizedfullnc", - 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