Date: Mon, 15 Jul 2024 12:38:19 GMT From: Andrew Turner <andrew@FreeBSD.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-branches@FreeBSD.org Subject: git: 750fbcc0603f - stable/13 - arm64: make SPE regs use ALT_NAME macro Message-ID: <202407151238.46FCcJXT060789@gitrepo.freebsd.org>
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The branch stable/13 has been updated by andrew: URL: https://cgit.FreeBSD.org/src/commit/?id=750fbcc0603fb9e7d9e4ee143e793674bf7649d7 commit 750fbcc0603fb9e7d9e4ee143e793674bf7649d7 Author: Zachary Leaf <zachary.leaf@arm.com> AuthorDate: 2024-05-10 15:59:00 +0000 Commit: Andrew Turner <andrew@FreeBSD.org> CommitDate: 2024-07-15 12:34:29 +0000 arm64: make SPE regs use ALT_NAME macro When the register is not defined in Armv8.0 i.e. added in a later extension, like SPE added in v8.2, the alternative name format of: S<op0>_<op1>_C<crn>_C<crm>_<op2> should be used; otherwise, calls to {READ,WRITE}_SPECIALREG() will fail. Use the MRS_REG_ALT_NAME() macro for SPE changing hex to decimal as required by the macro. Reviewed by: andrew Sponsored by: Arm Ltd Differential Revision: https://reviews.freebsd.org/D45171 (cherry picked from commit f7bdaa103eb8906fc999c7fd5e8d6af440e26e6c) --- sys/arm64/include/armreg.h | 132 ++++++++++++++++++++++++--------------------- 1 file changed, 72 insertions(+), 60 deletions(-) diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h index 92ad96550e56..1c9dfc1c19a7 100644 --- a/sys/arm64/include/armreg.h +++ b/sys/arm64/include/armreg.h @@ -1639,11 +1639,12 @@ /* PMBIDR_EL1 */ #define PMBIDR_EL1 MRS_REG(PMBIDR_EL1) -#define PMBIDR_EL1_op0 0x3 -#define PMBIDR_EL1_op1 0x0 -#define PMBIDR_EL1_CRn 0x9 -#define PMBIDR_EL1_CRm 0xa -#define PMBIDR_EL1_op2 0x7 +#define PMBIDR_EL1_REG MRS_REG_ALT_NAME(PMBIDR_EL1) +#define PMBIDR_EL1_op0 3 +#define PMBIDR_EL1_op1 0 +#define PMBIDR_EL1_CRn 9 +#define PMBIDR_EL1_CRm 10 +#define PMBIDR_EL1_op2 7 #define PMBIDR_Align_SHIFT 0 #define PMBIDR_Align_MASK (UL(0xf) << PMBIDR_Align_SHIFT) #define PMBIDR_P_SHIFT 4 @@ -1653,11 +1654,12 @@ /* PMBLIMITR_EL1 */ #define PMBLIMITR_EL1 MRS_REG(PMBLIMITR_EL1) -#define PMBLIMITR_EL1_op0 0x3 -#define PMBLIMITR_EL1_op1 0x0 -#define PMBLIMITR_EL1_CRn 0x9 -#define PMBLIMITR_EL1_CRm 0xa -#define PMBLIMITR_EL1_op2 0x0 +#define PMBLIMITR_EL1_REG MRS_REG_ALT_NAME(PMBLIMITR_EL1) +#define PMBLIMITR_EL1_op0 3 +#define PMBLIMITR_EL1_op1 0 +#define PMBLIMITR_EL1_CRn 9 +#define PMBLIMITR_EL1_CRm 10 +#define PMBLIMITR_EL1_op2 0 #define PMBLIMITR_E_SHIFT 0 #define PMBLIMITR_E (UL(0x1) << PMBLIMITR_E_SHIFT) #define PMBLIMITR_FM_SHIFT 1 @@ -1670,22 +1672,24 @@ /* PMBPTR_EL1 */ #define PMBPTR_EL1 MRS_REG(PMBPTR_EL1) -#define PMBPTR_EL1_op0 0x3 -#define PMBPTR_EL1_op1 0x0 -#define PMBPTR_EL1_CRn 0x9 -#define PMBPTR_EL1_CRm 0xa -#define PMBPTR_EL1_op2 0x1 +#define PMBPTR_EL1_REG MRS_REG_ALT_NAME(PMBPTR_EL1) +#define PMBPTR_EL1_op0 3 +#define PMBPTR_EL1_op1 0 +#define PMBPTR_EL1_CRn 9 +#define PMBPTR_EL1_CRm 10 +#define PMBPTR_EL1_op2 1 #define PMBPTR_PTR_SHIFT 0 #define PMBPTR_PTR_MASK \ (UL(0xffffffffffffffff) << PMBPTR_PTR_SHIFT) /* PMBSR_EL1 */ #define PMBSR_EL1 MRS_REG(PMBSR_EL1) -#define PMBSR_EL1_op0 0x3 -#define PMBSR_EL1_op1 0x0 -#define PMBSR_EL1_CRn 0x9 -#define PMBSR_EL1_CRm 0xa -#define PMBSR_EL1_op2 0x3 +#define PMBSR_EL1_REG MRS_REG_ALT_NAME(PMBSR_EL1) +#define PMBSR_EL1_op0 3 +#define PMBSR_EL1_op1 0 +#define PMBSR_EL1_CRn 9 +#define PMBSR_EL1_CRm 10 +#define PMBSR_EL1_op2 3 #define PMBSR_MSS_SHIFT 0 #define PMBSR_MSS_MASK (UL(0xffff) << PMBSR_MSS_SHIFT) #define PMBSR_COLL_SHIFT 16 @@ -1851,11 +1855,12 @@ /* PMSCR_EL1 */ #define PMSCR_EL1 MRS_REG(PMSCR_EL1) -#define PMSCR_EL1_op0 0x3 -#define PMSCR_EL1_op1 0x0 -#define PMSCR_EL1_CRn 0x9 -#define PMSCR_EL1_CRm 0x9 -#define PMSCR_EL1_op2 0x0 +#define PMSCR_EL1_REG MRS_REG_ALT_NAME(PMSCR_EL1) +#define PMSCR_EL1_op0 3 +#define PMSCR_EL1_op1 0 +#define PMSCR_EL1_CRn 9 +#define PMSCR_EL1_CRm 9 +#define PMSCR_EL1_op2 0 #define PMSCR_E0SPE_SHIFT 0 #define PMSCR_E0SPE (UL(0x1) << PMSCR_E0SPE_SHIFT) #define PMSCR_E1SPE_SHIFT 1 @@ -1880,19 +1885,21 @@ /* PMSEVFR_EL1 */ #define PMSEVFR_EL1 MRS_REG(PMSEVFR_EL1) -#define PMSEVFR_EL1_op0 0x3 -#define PMSEVFR_EL1_op1 0x0 -#define PMSEVFR_EL1_CRn 0x9 -#define PMSEVFR_EL1_CRm 0x9 -#define PMSEVFR_EL1_op2 0x5 +#define PMSEVFR_EL1_REG MRS_REG_ALT_NAME(PMSEVFR_EL1) +#define PMSEVFR_EL1_op0 3 +#define PMSEVFR_EL1_op1 0 +#define PMSEVFR_EL1_CRn 9 +#define PMSEVFR_EL1_CRm 9 +#define PMSEVFR_EL1_op2 5 /* PMSFCR_EL1 */ #define PMSFCR_EL1 MRS_REG(PMSFCR_EL1) -#define PMSFCR_EL1_op0 0x3 -#define PMSFCR_EL1_op1 0x0 -#define PMSFCR_EL1_CRn 0x9 -#define PMSFCR_EL1_CRm 0x9 -#define PMSFCR_EL1_op2 0x4 +#define PMSFCR_EL1_REG MRS_REG_ALT_NAME(PMSFCR_EL1) +#define PMSFCR_EL1_op0 3 +#define PMSFCR_EL1_op1 0 +#define PMSFCR_EL1_CRn 9 +#define PMSFCR_EL1_CRm 9 +#define PMSFCR_EL1_op2 4 #define PMSFCR_FE_SHIFT 0 #define PMSFCR_FE (UL(0x1) << PMSFCR_FE_SHIFT) #define PMSFCR_FT_SHIFT 1 @@ -1910,11 +1917,12 @@ /* PMSICR_EL1 */ #define PMSICR_EL1 MRS_REG(PMSICR_EL1) -#define PMSICR_EL1_op0 0x3 -#define PMSICR_EL1_op1 0x0 -#define PMSICR_EL1_CRn 0x9 -#define PMSICR_EL1_CRm 0x9 -#define PMSICR_EL1_op2 0x2 +#define PMSICR_EL1_REG MRS_REG_ALT_NAME(PMSICR_EL1) +#define PMSICR_EL1_op0 3 +#define PMSICR_EL1_op1 0 +#define PMSICR_EL1_CRn 9 +#define PMSICR_EL1_CRm 9 +#define PMSICR_EL1_op2 2 #define PMSICR_COUNT_SHIFT 0 #define PMSICR_COUNT_MASK (UL(0xffffffff) << PMSICR_COUNT_SHIFT) #define PMSICR_ECOUNT_SHIFT 56 @@ -1922,11 +1930,12 @@ /* PMSIDR_EL1 */ #define PMSIDR_EL1 MRS_REG(PMSIDR_EL1) -#define PMSIDR_EL1_op0 0x3 -#define PMSIDR_EL1_op1 0x0 -#define PMSIDR_EL1_CRn 0x9 -#define PMSIDR_EL1_CRm 0x9 -#define PMSIDR_EL1_op2 0x7 +#define PMSIDR_EL1_REG MRS_REG_ALT_NAME(PMSIDR_EL1) +#define PMSIDR_EL1_op0 3 +#define PMSIDR_EL1_op1 0 +#define PMSIDR_EL1_CRn 9 +#define PMSIDR_EL1_CRm 9 +#define PMSIDR_EL1_op2 7 #define PMSIDR_FE_SHIFT 0 #define PMSIDR_FE (UL(0x1) << PMSIDR_FE_SHIFT) #define PMSIDR_FT_SHIFT 1 @@ -1954,11 +1963,12 @@ /* PMSIRR_EL1 */ #define PMSIRR_EL1 MRS_REG(PMSIRR_EL1) -#define PMSIRR_EL1_op0 0x3 -#define PMSIRR_EL1_op1 0x0 -#define PMSIRR_EL1_CRn 0x9 -#define PMSIRR_EL1_CRm 0x9 -#define PMSIRR_EL1_op2 0x3 +#define PMSIRR_EL1_REG MRS_REG_ALT_NAME(PMSIRR_EL1) +#define PMSIRR_EL1_op0 3 +#define PMSIRR_EL1_op1 0 +#define PMSIRR_EL1_CRn 9 +#define PMSIRR_EL1_CRm 9 +#define PMSIRR_EL1_op2 3 #define PMSIRR_RND_SHIFT 0 #define PMSIRR_RND (UL(0x1) << PMSIRR_RND_SHIFT) #define PMSIRR_INTERVAL_SHIFT 8 @@ -1966,21 +1976,23 @@ /* PMSLATFR_EL1 */ #define PMSLATFR_EL1 MRS_REG(PMSLATFR_EL1) -#define PMSLATFR_EL1_op0 0x3 -#define PMSLATFR_EL1_op1 0x0 -#define PMSLATFR_EL1_CRn 0x9 -#define PMSLATFR_EL1_CRm 0x9 -#define PMSLATFR_EL1_op2 0x6 +#define PMSLATFR_EL1_REG MRS_REG_ALT_NAME(PMSLATFR_EL1) +#define PMSLATFR_EL1_op0 3 +#define PMSLATFR_EL1_op1 0 +#define PMSLATFR_EL1_CRn 9 +#define PMSLATFR_EL1_CRm 9 +#define PMSLATFR_EL1_op2 6 #define PMSLATFR_MINLAT_SHIFT 0 #define PMSLATFR_MINLAT_MASK (UL(0xfff) << PMSLATFR_MINLAT_SHIFT) /* PMSNEVFR_EL1 */ #define PMSNEVFR_EL1 MRS_REG(PMSNEVFR_EL1) -#define PMSNEVFR_EL1_op0 0x3 -#define PMSNEVFR_EL1_op1 0x0 -#define PMSNEVFR_EL1_CRn 0x9 -#define PMSNEVFR_EL1_CRm 0x9 -#define PMSNEVFR_EL1_op2 0x1 +#define PMSNEVFR_EL1_REG MRS_REG_ALT_NAME(PMSNEVFR_EL1) +#define PMSNEVFR_EL1_op0 3 +#define PMSNEVFR_EL1_op1 0 +#define PMSNEVFR_EL1_CRn 9 +#define PMSNEVFR_EL1_CRm 9 +#define PMSNEVFR_EL1_op2 1 /* PMSWINC_EL0 */ #define PMSWINC_EL0 MRS_REG(PMSWINC_EL0)
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