Date: Sat, 22 Jul 2000 08:04:24 +0200 (CEST) From: =?ISO-8859-1?Q?G=E9rard_Roudier?= <groudier@club-internet.fr> To: Mike Smith <msmith@FreeBSD.ORG> Cc: freebsd-alpha@FreeBSD.ORG Subject: Re: fxp0 hangs on a PC164 using STABLE Message-ID: <Pine.LNX.4.10.10007220740570.848-100000@linux.local> In-Reply-To: <200007220002.RAA01857@mass.osd.bsdi.com>
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On Fri, 21 Jul 2000, Mike Smith wrote: > > On Thu, 20 Jul 2000, Mike Smith wrote: > > > > > > It is my opinion. You may disagree but it will hard for anybody to > > > > convince me that I am wrong. ;-) > > > > > > On x86, it's very hard for you to be right; the CPU specification and bus > > > bridge behaviour both guarantee retirement of writes in order of issuance. > > > This combined with strong cache coherency makes barriers irrelevant on > > > this platform. > > > > Let a PCI device perform: > > STORE A > > STORE B > > > > Let the CPU perform and expect: > > LOAD B > > LOAD A > > > > Let some CPU speculative execution carry out to the system BUS: > > LOAD A > > LOAD B > > > > My reading of the the Intel docs didn't convince me that such reordering > > is not possible. > > > > Typically A is some indicator of an IO completion pushed to a completion > > queue and B is the associated status data. > > You've got those the wrong way around; A will be the status, and B the > indicator (since we have to assume the peripheral is correctly designed). Yes. It has been a typo from me, obviously. Just FYI, the SYM and the AIC7XXX should not get the LOADs reordered, in my opinion, since B (item extracted from the completion queue) is used as an index (or tag) to retrieve the IO data-structure and then the status data (A). An operand of the second LOAD depending on the first one insures no reordering will occur. Anyway, I have put the MB in the SYM for safety against any other weirdness I may have missed. :-) This is different in the NCR, that uses the host_status field of the nccb as completion flag, but tests against the xerr_status flag of the nccb for extended errors. Since these 2 informations are not written together atomically, the NCR falls into the above model, on paper. Just, the 2 LOADs are probably not close enough in the instruction stream for bad reordering to ever happen. > I don't believe that the x86 re-orders read operations (but I don't have > the P6 architecture manuals here to be certain). If it does, then to > remain compatible with older x86 processors, it would have to invalidate > the pipeline and re-fetch when the bus snoop code detected the STORE B. > > > > As far as other platforms are concerned, however, you're quite correct. > > > > Are you still so sure. ;-) > > Yes. x86 has so much seralised legacy baggage that it's a special case. You shouldn't, IMO, for Pi, i >= II, and some clones. :) > Everyone else needs help. 8) I probably fall into this category too. :) > > > There does need to be an extension to the busspace API to define a range > > > of host memory with a tag/handle pair for barrier activity. > > > > Hmmm... Barrier semantics vary so much between architectures that an > > unified semantic that also address device driver's concerns (not only > > CPU<->CPU) is either close to impossible or will just be extremally poor, > > in my opinion. > > I'm open to edification here, but I think that the ability to define the > sort of barrier operation required for a memory region and to then > invoke said barrier is about the best we can hope for. This looks to me the best complex and poor possible semantic. :) > > The drivers I maintain will always contain any stuff needed for them to be > > as correct as I want them to be, modulo my knowledge and competence on > > addressed platforms obviously. > > I don't think anyone could ask for any more than that. Thanks for the reply. Regards, Gérard. To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-alpha" in the body of the message
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