Date: Wed, 8 Jun 2011 08:12:15 +0000 (UTC) From: Andriy Gapon <avg@FreeBSD.org> To: cvs-src-old@freebsd.org Subject: cvs commit: src UPDATING src/sys/amd64/amd64 machdep.c mp_machdep.c src/sys/amd64/include smp.h src/sys/i386/i386 machdep.c mp_machdep.c src/sys/i386/include smp.h src/sys/pc98/pc98 machdep.c Message-ID: <201106080812.p588CeqT035634@repoman.freebsd.org>
next in thread | raw e-mail | index | archive | help
avg 2011-06-08 08:12:15 UTC
FreeBSD src repository
Modified files:
. UPDATING
sys/amd64/amd64 machdep.c mp_machdep.c
sys/amd64/include smp.h
sys/i386/i386 machdep.c mp_machdep.c
sys/i386/include smp.h
sys/pc98/pc98 machdep.c
Log:
SVN rev 222853 on 2011-06-08 08:12:15Z by avg
remove code for dynamic offlining/onlining of CPUs on x86
The code has definitely been broken for SCHED_ULE, which is a default
scheduler. It may have been broken for SCHED_4BSD in more subtle ways,
e.g. with manually configured CPU affinities and for interrupt devilery
purposes.
We still provide a way to disable individual CPUs or all hyperthreading
"twin" CPUs before SMP startup. See the UPDATING entry for details.
Interaction between building CPU topology and disabling CPUs still
remains fuzzy: topology is first built using all availble CPUs and then
the disabled CPUs should be "subtracted" from it. That doesn't work
well if the resulting topology becomes non-uniform.
This work is done in cooperation with Attilio Rao who in addition to
reviewing also provided parts of code.
PR: kern/145385
Discussed with: gcooper, ambrisko, mdf, sbruno
Reviewed by: attilio
Tested by: pho, pluknet
X-MFC after: never
Revision Changes Path
1.695 +17 -0 src/UPDATING
1.751 +4 -3 src/sys/amd64/amd64/machdep.c
1.344 +6 -165 src/sys/amd64/amd64/mp_machdep.c
1.102 +0 -1 src/sys/amd64/include/smp.h
1.733 +4 -3 src/sys/i386/i386/machdep.c
1.327 +6 -165 src/sys/i386/i386/mp_machdep.c
1.103 +0 -1 src/sys/i386/include/smp.h
1.447 +4 -3 src/sys/pc98/pc98/machdep.c
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?201106080812.p588CeqT035634>