Date: Tue, 18 Feb 2014 14:47:51 -0600 From: Stacey Son <sson@freebsd.org> To: Adrian Chadd <adrian@freebsd.org> Cc: "freebsd-mips@freebsd.org" <freebsd-mips@freebsd.org> Subject: Re: [RFC] 16K page size for kernel thread stack (patch) Message-ID: <EB4E2278-6E09-4495-8A0D-025A3AB4E4C7@freebsd.org> In-Reply-To: <CAJ-VmonLGOGChUohF7E3VBXFSohtAWPcADTxVo=8XreYosNu7A@mail.gmail.com> References: <FAC31FA0-26B0-468E-826F-1A17ECA6DA65@FreeBSD.org> <CAJ-VmonLGOGChUohF7E3VBXFSohtAWPcADTxVo=8XreYosNu7A@mail.gmail.com>
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On Feb 18, 2014, at 2:25 PM, Adrian Chadd <adrian@freebsd.org> wrote: > Hi! >=20 > On 18 February 2014 08:48, Stacey Son <sson@freebsd.org> wrote: >> Hi all: >>=20 >> For mips64 the current size of 8K is not enough for the kernel thread = stack. For more information, see: >>=20 >> http://www.freebsd.org/cgi/query-pr.cgi?pr=3D177876 >>=20 >> The following patch increases the size of the kernel thread stack to = 16K by using a single 16K sized page. See the patch at: >>=20 >> http://people.freebsd.org/~sson/mips/kstack/kstack_large_page.diff >=20 > Cool! Thanks for that. >=20 > I'm glad to see the supported pagesize enumeration code going into the > kernel. What do you think about committing just that bit to begin > with? Yes, it probes the supported pages sizes (or PageMasks) by writing all = one's to the PageMask register and then reading it back as suggested in = the MIPS architecture manual. If an implementation doesn't support all = the different page sizes then those bits should not stick. The various = page sizes that are supported are reported the same time the MMU = information is printed. =20 I store the PageMask probe result in cpuinfo. This way it is easy to = check to the make sure the page size that is needed is supported. Yes, it would be easy to check this in as a separate patch. > This looks like it touches shared code between mips32 and mips64. I'll > spin this up on a mips24k and mips74k (mips32r2) board soon to see if > it boots fine. Yes, I have only tested this on an ERL and Qemu. =20 Do any of your boards support the ULRI? (See my other patches.) The = ERL/Cavium Octeon CN5020 doesn't seem to support it. -stacey.
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