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Date:      Sun, 14 May 2017 21:33:01 +0000 (UTC)
From:      Marius Strobl <marius@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org
Subject:   svn commit: r318282 - head/sys/dev/sdhci
Message-ID:  <201705142133.v4ELX1kf043233@repo.freebsd.org>
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Author: marius
Date: Sun May 14 21:33:01 2017
New Revision: 318282
URL: https://svnweb.freebsd.org/changeset/base/318282

Log:
  - Unlike as in the PCI case, when attached to ACPI, Intel Bay Trail
    and Braswell eMMC and SDXC controllers share the same IDs. Like in
    the PCI case, Braswell eMMC needs the SDHCI_QUIRK_DATA_TIMEOUT_1MHZ
    quirk (see r311794 for the corresponding change to the sdhci(4) PCI
    PCI front-end), though. However, due to the shared ACPI IDs, this
    is trickier to do.
  - Intel Apollo Lake eMMC and SDXC controllers are affected by the
    APL18 ("Using 32-bit Addressing Mode With SD/eMMC Controller May
    Lead to Unpredictable System Behavior") silicon bug [1]. When this
    erratum hits, typically both SDHCI and XHCI controllers wedge.
    According to Intel, using ADMA2 with 64-bit addressing and 96-bit
    descriptors serves as a workaround. Until such times when sdhci(4)
    has ADMA2 support, flag DMA as broken for affected interfaces.
    This turns out to work around the problem, too, at the cost of
    performance.
  - In the sdhci(4) ACPI front-end, probe the Intel Apollo Lake eMMC
    and SDXC controllers, too.
  
  1: http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/pentium-celeron-n-series-j-series-datasheet-spec-update.pdf

Modified:
  head/sys/dev/sdhci/sdhci_acpi.c
  head/sys/dev/sdhci/sdhci_pci.c

Modified: head/sys/dev/sdhci/sdhci_acpi.c
==============================================================================
--- head/sys/dev/sdhci/sdhci_acpi.c	Sun May 14 21:18:01 2017	(r318281)
+++ head/sys/dev/sdhci/sdhci_acpi.c	Sun May 14 21:33:01 2017	(r318282)
@@ -57,25 +57,39 @@ static const struct sdhci_acpi_device {
 	const char	*desc;
 	u_int		quirks;
 } sdhci_acpi_devices[] = {
-	{ "80860F14",	1,	"Intel Bay Trail eMMC 4.5 Controller",
+	{ "80860F14",	1, "Intel Bay Trail/Braswell eMMC 4.5/4.5.1 Controller",
 	    SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE |
 	    SDHCI_QUIRK_INTEL_POWER_UP_RESET |
 	    SDHCI_QUIRK_WAIT_WHILE_BUSY |
 	    SDHCI_QUIRK_MMC_DDR52 |
 	    SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 |
 	    SDHCI_QUIRK_PRESET_VALUE_BROKEN },
-	{ "80860F14",	3,	"Intel Bay Trail SDXC Controller",
+	{ "80860F14",	3, "Intel Bay Trail/Braswell SDXC Controller",
 	    SDHCI_QUIRK_WAIT_WHILE_BUSY |
 	    SDHCI_QUIRK_PRESET_VALUE_BROKEN },
-	{ "80860F16",	0,	"Intel Bay Trail SDXC Controller",
+	{ "80860F16",	0, "Intel Bay Trail/Braswell SDXC Controller",
 	    SDHCI_QUIRK_WAIT_WHILE_BUSY |
 	    SDHCI_QUIRK_PRESET_VALUE_BROKEN },
+	{ "80865ACA",	0, "Intel Apollo Lake SDXC Controller",
+	    SDHCI_QUIRK_BROKEN_DMA |	/* APL18 erratum */
+	    SDHCI_QUIRK_WAIT_WHILE_BUSY |
+	    SDHCI_QUIRK_PRESET_VALUE_BROKEN },
+	{ "80865ACC",	0, "Intel Apollo Lake eMMC 5.0 Controller",
+	    SDHCI_QUIRK_BROKEN_DMA |	/* APL18 erratum */
+	    SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE |
+	    SDHCI_QUIRK_INTEL_POWER_UP_RESET |
+	    SDHCI_QUIRK_WAIT_WHILE_BUSY |
+	    SDHCI_QUIRK_MMC_DDR52 |
+	    SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 |
+	    SDHCI_QUIRK_PRESET_VALUE_BROKEN },
 	{ NULL, 0, NULL, 0}
 };
 
 static char *sdhci_ids[] = {
 	"80860F14",
 	"80860F16",
+	"80865ACA",
+	"80865ACC",
 	NULL
 };
 
@@ -249,6 +263,11 @@ sdhci_acpi_attach(device_t dev)
 		return (ENOMEM);
 	}
 
+	/* Intel Braswell eMMC 4.5.1 controller quirk */
+	if (strcmp(acpi_dev->hid, "80860F14") == 0 && acpi_dev->uid == 1 &&
+	    SDHCI_READ_4(dev, &sc->slot, SDHCI_CAPABILITIES) == 0x446cc8b2 &&
+	    SDHCI_READ_4(dev, &sc->slot, SDHCI_CAPABILITIES2) == 0x00000807)
+		sc->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_1MHZ;
 	sc->quirks &= ~sdhci_quirk_clear;
 	sc->quirks |= sdhci_quirk_set;
 	sc->slot.quirks = sc->quirks;

Modified: head/sys/dev/sdhci/sdhci_pci.c
==============================================================================
--- head/sys/dev/sdhci/sdhci_pci.c	Sun May 14 21:18:01 2017	(r318281)
+++ head/sys/dev/sdhci/sdhci_pci.c	Sun May 14 21:33:01 2017	(r318282)
@@ -132,9 +132,11 @@ static const struct sdhci_device {
 	    SDHCI_QUIRK_WAIT_WHILE_BUSY |
 	    SDHCI_QUIRK_PRESET_VALUE_BROKEN },
 	{ 0x5aca8086,	0xffff,	"Intel Apollo Lake SDXC Controller",
+	    SDHCI_QUIRK_BROKEN_DMA |	/* APL18 erratum */
 	    SDHCI_QUIRK_WAIT_WHILE_BUSY |
 	    SDHCI_QUIRK_PRESET_VALUE_BROKEN },
 	{ 0x5acc8086,	0xffff,	"Intel Apollo Lake eMMC 5.0 Controller",
+	    SDHCI_QUIRK_BROKEN_DMA |	/* APL18 erratum */
 	    SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE |
 	    SDHCI_QUIRK_INTEL_POWER_UP_RESET |
 	    SDHCI_QUIRK_WAIT_WHILE_BUSY |
@@ -340,6 +342,7 @@ sdhci_pci_attach(device_t dev)
 	}
 	sc->quirks &= ~sdhci_quirk_clear;
 	sc->quirks |= sdhci_quirk_set;
+
 	/* Some controllers need to be bumped into the right mode. */
 	if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY)
 		sdhci_lower_frequency(dev);

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