Date: Thu, 12 Aug 2010 09:44:47 +0530 From: "Jayachandran C." <c.jayachandran@gmail.com> To: Juli Mallett <jmallett@freebsd.org>, Neel Natu <neelnatu@gmail.com>, "M. Warner Losh" <imp@bsdimp.com>, freebsd-mips@freebsd.org Subject: SMP support for n64 patch. Message-ID: <AANLkTimQVoRTc3CHNGHNAS2-PRqiZ8BiStekp6tj1Qc4@mail.gmail.com>
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[-- Attachment #1 --]
I've attached a patch that enables SMP support for N64 builds (I can
get XLR come up multi-user with 32 cpus with this).
I ended up making KX bit in status register set when you are in
userspace, since the PCPU area is now mapped in XKSEG. The PCPU area
needs to be accessed in I have reverted the earlier change that
enabled KX on kernel entry from userspace since that is no longer
needed.
Please let me know your comments.
JC.
[-- Attachment #2 --]
Index: sys/mips/mips/vm_machdep.c
===================================================================
--- sys/mips/mips/vm_machdep.c (revision 211066)
+++ sys/mips/mips/vm_machdep.c (working copy)
@@ -419,7 +419,7 @@
#if defined(__mips_n32)
td->td_frame->sr |= MIPS_SR_PX;
#elif defined(__mips_n64)
- td->td_frame->sr |= MIPS_SR_PX | MIPS_SR_UX;
+ td->td_frame->sr |= MIPS_SR_PX | MIPS_SR_UX | MIPS_SR_KX;
#endif
#ifdef CPU_CNMIPS
tf->sr |= MIPS_SR_INT_IE | MIPS_SR_COP_0_BIT | MIPS_SR_PX | MIPS_SR_UX |
Index: sys/mips/mips/exception.S
===================================================================
--- sys/mips/mips/exception.S (revision 211066)
+++ sys/mips/mips/exception.S (working copy)
@@ -434,12 +434,6 @@
/*
* Save all of the registers except for the kernel temporaries in u.u_pcb.
*/
- mfc0 k0, MIPS_COP_0_STATUS
- HAZARD_DELAY
-#ifdef __mips_n64
- ori k1, k0, MIPS_SR_KX
- mtc0 k1, MIPS_COP_0_STATUS
-#endif
GET_CPU_PCPU(k1)
PTR_L k1, PC_CURPCB(k1)
SAVE_U_PCB_REG(AT, AST, k1)
@@ -457,7 +451,7 @@
SAVE_U_PCB_REG(t2, T2, k1)
SAVE_U_PCB_REG(t3, T3, k1)
SAVE_U_PCB_REG(ta0, TA0, k1)
- move a0, k0 # First arg is the status reg.
+ mfc0 a0, MIPS_COP_0_STATUS # First arg is the status reg.
SAVE_U_PCB_REG(ta1, TA1, k1)
SAVE_U_PCB_REG(ta2, TA2, k1)
SAVE_U_PCB_REG(ta3, TA3, k1)
@@ -656,12 +650,6 @@
* Save the relevant user registers into the u.u_pcb struct.
* We don't need to save s0 - s8 because the compiler does it for us.
*/
- mfc0 k0, MIPS_COP_0_STATUS
- HAZARD_DELAY
-#ifdef __mips_n64
- ori k1, k0, MIPS_SR_KX
- mtc0 k1, MIPS_COP_0_STATUS
-#endif
GET_CPU_PCPU(k1)
PTR_L k1, PC_CURPCB(k1)
SAVE_U_PCB_REG(AT, AST, k1)
@@ -700,7 +688,7 @@
mflo v0 # get lo/hi late to avoid stall
mfhi v1
- move a0, k0
+ mfc0 a0, MIPS_COP_0_STATUS
mfc0 a1, MIPS_COP_0_CAUSE
MFC0 a3, MIPS_COP_0_EXC_PC
SAVE_U_PCB_REG(v0, MULLO, k1)
Index: sys/mips/mips/mpboot.S
===================================================================
--- sys/mips/mips/mpboot.S (revision 211066)
+++ sys/mips/mips/mpboot.S (working copy)
@@ -36,7 +36,8 @@
.set noat
.set noreorder
-#ifdef CPU_CNMIPS
+/* XXX move this to a header file */
+#if defined(CPU_CNMIPS)
#define CLEAR_STATUS \
mfc0 a0, MIPS_COP_0_STATUS ;\
li a2, (MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX) ; \
@@ -44,6 +45,10 @@
li a2, ~(MIPS_SR_INT_IE | MIPS_SR_EXL | SR_KSU_USER | MIPS_SR_BEV) ; \
and a0, a0, a2 ; \
mtc0 a0, MIPS_COP_0_STATUS
+#elif defined(__mips_n64)
+#define CLEAR_STATUS \
+ li a0, (MIPS_SR_KX | MIPS_SR_UX) ; \
+ mtc0 a0, MIPS_COP_0_STATUS
#else
#define CLEAR_STATUS \
mtc0 zero, MIPS_COP_0_STATUS
Index: sys/mips/mips/pm_machdep.c
===================================================================
--- sys/mips/mips/pm_machdep.c (revision 211066)
+++ sys/mips/mips/pm_machdep.c (working copy)
@@ -517,7 +517,7 @@
#if defined(__mips_n32)
td->td_frame->sr |= MIPS_SR_PX;
#elif defined(__mips_n64)
- td->td_frame->sr |= MIPS_SR_PX | MIPS_SR_UX;
+ td->td_frame->sr |= MIPS_SR_PX | MIPS_SR_UX | MIPS_SR_KX;
#endif
#ifdef CPU_CNMIPS
td->td_frame->sr |= MIPS_SR_COP_2_BIT | MIPS_SR_PX | MIPS_SR_UX |
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