Date: Tue, 25 Jul 2006 21:08:27 GMT From: Sam Leffler <sam@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 102412 for review Message-ID: <200607252108.k6PL8RI0009706@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=102412 Change 102412 by sam@sam_ebb on 2006/07/25 21:08:10 Checkpoint bus space changes: o add stream members and associated glop to struct bus_space o switch struct initializations to c99 syntax o start pci support; 4-byte r/w works well enough for ath to run but need to fix 1+2 byte ops Affected files ... .. //depot/projects/arm/src/sys/arm/include/bus.h#4 edit .. //depot/projects/arm/src/sys/arm/xscale/ixp425/ixp425_a4x_space.c#2 edit .. //depot/projects/arm/src/sys/arm/xscale/ixp425/ixp425_pci_space.c#2 edit .. //depot/projects/arm/src/sys/arm/xscale/ixp425/ixp425_space.c#2 edit Differences ... ==== //depot/projects/arm/src/sys/arm/include/bus.h#4 (text+ko) ==== @@ -195,6 +195,61 @@ void (*bs_c_8) (void *, bus_space_handle_t, bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t); + /* read stream (single) */ + u_int8_t (*bs_r_1_s) (void *, bus_space_handle_t, bus_size_t); + u_int16_t (*bs_r_2_s) (void *, bus_space_handle_t, bus_size_t); + u_int32_t (*bs_r_4_s) (void *, bus_space_handle_t, bus_size_t); + u_int64_t (*bs_r_8_s) (void *, bus_space_handle_t, bus_size_t); + + /* read multiple stream */ + void (*bs_rm_1_s) (void *, bus_space_handle_t, bus_size_t, + u_int8_t *, bus_size_t); + void (*bs_rm_2_s) (void *, bus_space_handle_t, bus_size_t, + u_int16_t *, bus_size_t); + void (*bs_rm_4_s) (void *, bus_space_handle_t, + bus_size_t, u_int32_t *, bus_size_t); + void (*bs_rm_8_s) (void *, bus_space_handle_t, + bus_size_t, u_int64_t *, bus_size_t); + + /* read region stream */ + void (*bs_rr_1_s) (void *, bus_space_handle_t, + bus_size_t, u_int8_t *, bus_size_t); + void (*bs_rr_2_s) (void *, bus_space_handle_t, + bus_size_t, u_int16_t *, bus_size_t); + void (*bs_rr_4_s) (void *, bus_space_handle_t, + bus_size_t, u_int32_t *, bus_size_t); + void (*bs_rr_8_s) (void *, bus_space_handle_t, + bus_size_t, u_int64_t *, bus_size_t); + + /* write stream (single) */ + void (*bs_w_1_s) (void *, bus_space_handle_t, + bus_size_t, u_int8_t); + void (*bs_w_2_s) (void *, bus_space_handle_t, + bus_size_t, u_int16_t); + void (*bs_w_4_s) (void *, bus_space_handle_t, + bus_size_t, u_int32_t); + void (*bs_w_8_s) (void *, bus_space_handle_t, + bus_size_t, u_int64_t); + + /* write multiple stream */ + void (*bs_wm_1_s) (void *, bus_space_handle_t, + bus_size_t, const u_int8_t *, bus_size_t); + void (*bs_wm_2_s) (void *, bus_space_handle_t, + bus_size_t, const u_int16_t *, bus_size_t); + void (*bs_wm_4_s) (void *, bus_space_handle_t, + bus_size_t, const u_int32_t *, bus_size_t); + void (*bs_wm_8_s) (void *, bus_space_handle_t, + bus_size_t, const u_int64_t *, bus_size_t); + + /* write region stream */ + void (*bs_wr_1_s) (void *, bus_space_handle_t, + bus_size_t, const u_int8_t *, bus_size_t); + void (*bs_wr_2_s) (void *, bus_space_handle_t, + bus_size_t, const u_int16_t *, bus_size_t); + void (*bs_wr_4_s) (void *, bus_space_handle_t, + bus_size_t, const u_int32_t *, bus_size_t); + void (*bs_wr_8_s) (void *, bus_space_handle_t, + bus_size_t, const u_int64_t *, bus_size_t); }; @@ -215,6 +270,14 @@ #define __bs_copy(sz, t, h1, o1, h2, o2, cnt) \ (*(t)->__bs_opname(c,sz))((t)->bs_cookie, h1, o1, h2, o2, cnt) +#define __bs_opname_s(op,size) __bs_c(__bs_c(__bs_c(__bs_c(bs_,op),_),size),_s) +#define __bs_rs_s(sz, t, h, o) \ + (*(t)->__bs_opname_s(r,sz))((t)->bs_cookie, h, o) +#define __bs_ws_s(sz, t, h, o, v) \ + (*(t)->__bs_opname_s(w,sz))((t)->bs_cookie, h, o, v) +#define __bs_nonsingle_s(type, sz, t, h, o, a, c) \ + (*(t)->__bs_opname_s(type,sz))((t)->bs_cookie, h, o, a, c) + /* * Mapping and unmapping operations. @@ -253,6 +316,10 @@ #define bus_space_read_4(t, h, o) __bs_rs(4,(t),(h),(o)) #define bus_space_read_8(t, h, o) __bs_rs(8,(t),(h),(o)) +#define bus_space_read_stream_1(t, h, o) __bs_rs_s(1,(t), (h), (o)) +#define bus_space_read_stream_2(t, h, o) __bs_rs_s(2,(t), (h), (o)) +#define bus_space_read_stream_4(t, h, o) __bs_rs_s(4,(t), (h), (o)) +#define bus_space_read_stream_8(t, h, o) __bs_rs_s(8,8,(t),(h),(o)) /* * Bus read multiple operations. @@ -266,6 +333,15 @@ #define bus_space_read_multi_8(t, h, o, a, c) \ __bs_nonsingle(rm,8,(t),(h),(o),(a),(c)) +#define bus_space_read_multi_stream_1(t, h, o, a, c) \ + __bs_nonsingle_s(rm,1,(t),(h),(o),(a),(c)) +#define bus_space_read_multi_stream_2(t, h, o, a, c) \ + __bs_nonsingle_s(rm,2,(t),(h),(o),(a),(c)) +#define bus_space_read_multi_stream_4(t, h, o, a, c) \ + __bs_nonsingle_s(rm,4,(t),(h),(o),(a),(c)) +#define bus_space_read_multi_stream_8(t, h, o, a, c) \ + __bs_nonsingle_s(rm,8,(t),(h),(o),(a),(c)) + /* * Bus read region operations. @@ -279,6 +355,15 @@ #define bus_space_read_region_8(t, h, o, a, c) \ __bs_nonsingle(rr,8,(t),(h),(o),(a),(c)) +#define bus_space_read_region_stream_1(t, h, o, a, c) \ + __bs_nonsingle_s(rr,1,(t),(h),(o),(a),(c)) +#define bus_space_read_region_stream_2(t, h, o, a, c) \ + __bs_nonsingle_s(rr,2,(t),(h),(o),(a),(c)) +#define bus_space_read_region_stream_4(t, h, o, a, c) \ + __bs_nonsingle_s(rr,4,(t),(h),(o),(a),(c)) +#define bus_space_read_region_stream_8(t, h, o, a, c) \ + __bs_nonsingle_s(rr,8,(t),(h),(o),(a),(c)) + /* * Bus write (single) operations. @@ -288,7 +373,12 @@ #define bus_space_write_4(t, h, o, v) __bs_ws(4,(t),(h),(o),(v)) #define bus_space_write_8(t, h, o, v) __bs_ws(8,(t),(h),(o),(v)) +#define bus_space_write_stream_1(t, h, o, v) __bs_ws_s(1,(t),(h),(o),(v)) +#define bus_space_write_stream_2(t, h, o, v) __bs_ws_s(2,(t),(h),(o),(v)) +#define bus_space_write_stream_4(t, h, o, v) __bs_ws_s(4,(t),(h),(o),(v)) +#define bus_space_write_stream_8(t, h, o, v) __bs_ws_s(8,(t),(h),(o),(v)) + /* * Bus write multiple operations. */ @@ -301,6 +391,15 @@ #define bus_space_write_multi_8(t, h, o, a, c) \ __bs_nonsingle(wm,8,(t),(h),(o),(a),(c)) +#define bus_space_write_multi_stream_1(t, h, o, a, c) \ + __bs_nonsingle_s(wm,1,(t),(h),(o),(a),(c)) +#define bus_space_write_multi_stream_2(t, h, o, a, c) \ + __bs_nonsingle_s(wm,2,(t),(h),(o),(a),(c)) +#define bus_space_write_multi_stream_4(t, h, o, a, c) \ + __bs_nonsingle_s(wm,4,(t),(h),(o),(a),(c)) +#define bus_space_write_multi_stream_8(t, h, o, a, c) \ + __bs_nonsingle_s(wm,8,(t),(h),(o),(a),(c)) + /* * Bus write region operations. @@ -314,7 +413,16 @@ #define bus_space_write_region_8(t, h, o, a, c) \ __bs_nonsingle(wr,8,(t),(h),(o),(a),(c)) +#define bus_space_write_region_stream_1(t, h, o, a, c) \ + __bs_nonsingle_s(wr,1,(t),(h),(o),(a),(c)) +#define bus_space_write_region_stream_2(t, h, o, a, c) \ + __bs_nonsingle_s(wr,2,(t),(h),(o),(a),(c)) +#define bus_space_write_region_stream_4(t, h, o, a, c) \ + __bs_nonsingle_s(wr,4,(t),(h),(o),(a),(c)) +#define bus_space_write_region_stream_8(t, h, o, a, c) \ + __bs_nonsingle_s(wr,8,(t),(h),(o),(a),(c)) + /* * Set multiple operations. */ @@ -403,6 +511,18 @@ u_int64_t __bs_c(f,_bs_r_8) (void *t, bus_space_handle_t bsh, \ bus_size_t offset); +#define bs_r_1_s_proto(f) \ +u_int8_t __bs_c(f,_bs_r_1_s) (void *t, bus_space_handle_t bsh, \ + bus_size_t offset); + +#define bs_r_2_s_proto(f) \ +u_int16_t __bs_c(f,_bs_r_2_s) (void *t, bus_space_handle_t bsh, \ + bus_size_t offset); + +#define bs_r_4_s_proto(f) \ +u_int32_t __bs_c(f,_bs_r_4_s) (void *t, bus_space_handle_t bsh, \ + bus_size_t offset); + #define bs_w_1_proto(f) \ void __bs_c(f,_bs_w_1) (void *t, bus_space_handle_t bsh, \ bus_size_t offset, u_int8_t value); @@ -419,6 +539,18 @@ void __bs_c(f,_bs_w_8) (void *t, bus_space_handle_t bsh, \ bus_size_t offset, u_int64_t value); +#define bs_w_1_s_proto(f) \ +void __bs_c(f,_bs_w_1_s) (void *t, bus_space_handle_t bsh, \ + bus_size_t offset, u_int8_t value); + +#define bs_w_2_s_proto(f) \ +void __bs_c(f,_bs_w_2_s) (void *t, bus_space_handle_t bsh, \ + bus_size_t offset, u_int16_t value); + +#define bs_w_4_s_proto(f) \ +void __bs_c(f,_bs_w_4_s) (void *t, bus_space_handle_t bsh, \ + bus_size_t offset, u_int32_t value); + #define bs_rm_1_proto(f) \ void __bs_c(f,_bs_rm_1) (void *t, bus_space_handle_t bsh, \ bus_size_t offset, u_int8_t *addr, bus_size_t count); @@ -547,10 +679,16 @@ bs_r_2_proto(f); \ bs_r_4_proto(f); \ bs_r_8_proto(f); \ +bs_r_1_s_proto(f); \ +bs_r_2_s_proto(f); \ +bs_r_4_s_proto(f); \ bs_w_1_proto(f); \ bs_w_2_proto(f); \ bs_w_4_proto(f); \ bs_w_8_proto(f); \ +bs_w_1_s_proto(f); \ +bs_w_2_s_proto(f); \ +bs_w_4_s_proto(f); \ bs_rm_1_proto(f); \ bs_rm_2_proto(f); \ bs_rm_4_proto(f); \ @@ -589,33 +727,6 @@ #define BUS_SPACE_MAXSIZE_32BIT 0xFFFFFFFF #define BUS_SPACE_MAXSIZE 0xFFFFFFFF -/* XXX: is this right ? */ -#define bus_space_read_stream_1(t, h, o) bus_space_read_1((t), (h), (o)) -#define bus_space_read_stream_2(t, h, o) bus_space_read_2((t), (h), (o)) -#define bus_space_read_stream_4(t, h, o) bus_space_read_4((t), (h), (o)) - -#define bus_space_read_multi_stream_1(t, h, o, a, c) \ - bus_space_read_multi_1((t), (h), (o), (a), (c)) -#define bus_space_read_multi_stream_2(t, h, o, a, c) \ - bus_space_read_multi_2((t), (h), (o), (a), (c)) -#define bus_space_read_multi_stream_4(t, h, o, a, c) \ - bus_space_read_multi_4((t), (h), (o), (a), (c)) - -#define bus_space_write_stream_1(t, h, o, v) \ - bus_space_write_1((t), (h), (o), (v)) -#define bus_space_write_stream_2(t, h, o, v) \ - bus_space_write_2((t), (h), (o), (v)) -#define bus_space_write_stream_4(t, h, o, v) \ - bus_space_write_4((t), (h), (o), (v)) - -#define bus_space_write_multi_stream_1(t, h, o, a, c) \ - bus_space_write_multi_1((t), (h), (o), (a), (c)) -#define bus_space_write_multi_stream_2(t, h, o, a, c) \ - bus_space_write_multi_2((t), (h), (o), (a), (c)) -#define bus_space_write_multi_stream_4(t, h, o, a, c) \ - bus_space_write_multi_4((t), (h), (o), (a), (c)) - - #include <machine/bus_dma.h> #endif /* _MACHINE_BUS_H_ */ ==== //depot/projects/arm/src/sys/arm/xscale/ixp425/ixp425_a4x_space.c#2 (text+ko) ==== @@ -67,71 +67,50 @@ struct bus_space ixp425_a4x_bs_tag = { /* cookie */ - (void *) 0, + .bs_cookie = (void *) 0, /* mapping/unmapping */ - ixp425_bs_map, - ixp425_bs_unmap, - ixp425_bs_subregion, + .bs_map = ixp425_bs_map, + .bs_unmap = ixp425_bs_unmap, + .bs_subregion = ixp425_bs_subregion, /* allocation/deallocation */ - ixp425_bs_alloc, /* not implemented */ - ixp425_bs_free, /* not implemented */ + .bs_alloc = ixp425_bs_alloc, /* XXX not implemented */ + .bs_free = ixp425_bs_free, /* XXX not implemented */ /* barrier */ - ixp425_bs_barrier, + .bs_barrier = ixp425_bs_barrier, /* read (single) */ - a4x_bs_r_1, - a4x_bs_r_2, - a4x_bs_r_4, - NULL, + .bs_r_1 = a4x_bs_r_1, + .bs_r_2 = a4x_bs_r_2, + .bs_r_4 = a4x_bs_r_4, /* read multiple */ - a4x_bs_rm_1, - a4x_bs_rm_2, - NULL, - NULL, + .bs_rm_1 = a4x_bs_rm_1, + .bs_rm_2 = a4x_bs_rm_2, /* read region */ - NULL, - NULL, - NULL, - NULL, + /* XXX not implemented */ /* write (single) */ - a4x_bs_w_1, - a4x_bs_w_2, - a4x_bs_w_4, - NULL, + .bs_w_1 = a4x_bs_w_1, + .bs_w_2 = a4x_bs_w_2, + .bs_w_4 = a4x_bs_w_4, /* write multiple */ - a4x_bs_wm_1, - a4x_bs_wm_2, - NULL, - NULL, + .bs_wm_1 = a4x_bs_wm_1, + .bs_wm_2 = a4x_bs_wm_2, /* write region */ - NULL, - NULL, - NULL, - NULL, + /* XXX not implemented */ /* set multiple */ - NULL, - NULL, - NULL, - NULL, + /* XXX not implemented */ /* set region */ - NULL, - NULL, - NULL, - NULL, + /* XXX not implemented */ /* copy */ - NULL, - NULL, - NULL, - NULL, + /* XXX not implemented */ }; ==== //depot/projects/arm/src/sys/arm/xscale/ixp425/ixp425_pci_space.c#2 (text+ko) ==== @@ -43,6 +43,7 @@ #include <sys/param.h> #include <sys/systm.h> #include <sys/bus.h> +#include <sys/endian.h> #include <machine/pcb.h> @@ -71,130 +72,137 @@ bs_protos(ixp425_pci_mem); /* special I/O functions */ -inline u_int8_t _pci_io_bs_r_1(void *, bus_space_handle_t, bus_size_t); -inline u_int16_t _pci_io_bs_r_2(void *, bus_space_handle_t, bus_size_t); -inline u_int32_t _pci_io_bs_r_4(void *, bus_space_handle_t, bus_size_t); +static u_int8_t _pci_io_bs_r_1(void *, bus_space_handle_t, bus_size_t); +static u_int16_t _pci_io_bs_r_2(void *, bus_space_handle_t, bus_size_t); +static u_int32_t _pci_io_bs_r_4(void *, bus_space_handle_t, bus_size_t); + +static void _pci_io_bs_w_1(void *, bus_space_handle_t, bus_size_t, u_int8_t); +static void _pci_io_bs_w_2(void *, bus_space_handle_t, bus_size_t, u_int16_t); +static void _pci_io_bs_w_4(void *, bus_space_handle_t, bus_size_t, u_int32_t); + +#ifdef __ARMEB__ +static u_int8_t _pci_io_bs_r_1_s(void *, bus_space_handle_t, bus_size_t); +static u_int16_t _pci_io_bs_r_2_s(void *, bus_space_handle_t, bus_size_t); +static u_int32_t _pci_io_bs_r_4_s(void *, bus_space_handle_t, bus_size_t); + +static void _pci_io_bs_w_1_s(void *, bus_space_handle_t, bus_size_t, u_int8_t); +static void _pci_io_bs_w_2_s(void *, bus_space_handle_t, bus_size_t, u_int16_t); +static void _pci_io_bs_w_4_s(void *, bus_space_handle_t, bus_size_t, u_int32_t); -inline void _pci_io_bs_w_1(void *, bus_space_handle_t, bus_size_t, u_int8_t); -inline void _pci_io_bs_w_2(void *, bus_space_handle_t, bus_size_t, u_int16_t); -inline void _pci_io_bs_w_4(void *, bus_space_handle_t, bus_size_t, u_int32_t); +static u_int8_t _pci_mem_bs_r_1(void *, bus_space_handle_t, bus_size_t); +static u_int16_t _pci_mem_bs_r_2(void *, bus_space_handle_t, bus_size_t); +static u_int32_t _pci_mem_bs_r_4(void *, bus_space_handle_t, bus_size_t); -struct bus_space ixp425_pci_bs_tag_template = { - /* cookie */ - (void *) 0, +static void _pci_mem_bs_w_1(void *, bus_space_handle_t, bus_size_t, u_int8_t); +static void _pci_mem_bs_w_2(void *, bus_space_handle_t, bus_size_t, u_int16_t); +static void _pci_mem_bs_w_4(void *, bus_space_handle_t, bus_size_t, u_int32_t); +#endif +struct bus_space ixp425_pci_io_bs_tag_template = { /* mapping/unmapping */ - NULL, - NULL, - ixp425_pci_bs_subregion, + .bs_map = ixp425_pci_io_bs_map, + .bs_unmap = ixp425_pci_io_bs_unmap, + .bs_subregion = ixp425_pci_bs_subregion, - /* allocation/deallocation */ - NULL, - NULL, + .bs_alloc = ixp425_pci_io_bs_alloc, + .bs_free = ixp425_pci_io_bs_free, /* barrier */ - ixp425_pci_bs_barrier, + .bs_barrier = ixp425_pci_bs_barrier, + /* + * IXP425 processor does not have PCI I/O windows + */ /* read (single) */ - NULL, - NULL, - NULL, - NULL, - - /* read multiple */ - NULL, - NULL, - NULL, - NULL, - - /* read region */ - NULL, - NULL, - NULL, - NULL, + .bs_r_1 = _pci_io_bs_r_1, + .bs_r_2 = _pci_io_bs_r_2, + .bs_r_4 = _pci_io_bs_r_4, /* write (single) */ - NULL, - NULL, - NULL, - NULL, + .bs_w_1 = _pci_io_bs_w_1, + .bs_w_2 = _pci_io_bs_w_2, + .bs_w_4 = _pci_io_bs_w_4, - /* write multiple */ - NULL, - NULL, - NULL, - NULL, +#ifdef __ARMEB__ + .bs_r_1_s = _pci_io_bs_r_1_s, + .bs_r_2_s = _pci_io_bs_r_2_s, + .bs_r_4_s = _pci_io_bs_r_4_s, - /* write region */ - NULL, - NULL, - NULL, - NULL, + .bs_w_1_s = _pci_io_bs_w_1_s, + .bs_w_2_s = _pci_io_bs_w_2_s, + .bs_w_4_s = _pci_io_bs_w_4_s, +#else + .bs_r_1_s = _pci_io_bs_r_1, + .bs_r_2_s = _pci_io_bs_r_2, + .bs_r_4_s = _pci_io_bs_r_4, - /* set multiple */ - NULL, - NULL, - NULL, - NULL, - - /* set region */ - NULL, - NULL, - NULL, - NULL, - - /* copy */ - NULL, - NULL, - NULL, - NULL, + .bs_w_1_s = _pci_io_bs_w_1, + .bs_w_2_s = _pci_io_bs_w_2, + .bs_w_4_s = _pci_io_bs_w_4, +#endif }; void ixp425_io_bs_init(bus_space_tag_t bs, void *cookie) { - *bs = ixp425_pci_bs_tag_template; + *bs = ixp425_pci_io_bs_tag_template; bs->bs_cookie = cookie; +} + +struct bus_space ixp425_pci_mem_bs_tag_template = { + /* mapping/unmapping */ + .bs_map = ixp425_pci_mem_bs_map, + .bs_unmap = ixp425_pci_mem_bs_unmap, + .bs_subregion = ixp425_pci_bs_subregion, + + .bs_alloc = ixp425_pci_mem_bs_alloc, + .bs_free = ixp425_pci_mem_bs_free, + + /* barrier */ + .bs_barrier = ixp425_pci_bs_barrier, + +#ifdef __ARMEB__ + /* read (single) */ + .bs_r_1 = _pci_mem_bs_r_1, + .bs_r_2 = _pci_mem_bs_r_2, + .bs_r_4 = _pci_mem_bs_r_4, + + .bs_r_1_s = ixp425_pci_mem_bs_r_1, + .bs_r_2_s = ixp425_pci_mem_bs_r_2, + .bs_r_4_s = ixp425_pci_mem_bs_r_4, - bs->bs_map = ixp425_pci_io_bs_map; - bs->bs_unmap = ixp425_pci_io_bs_unmap; - bs->bs_alloc = ixp425_pci_io_bs_alloc; - bs->bs_free = ixp425_pci_io_bs_free; + /* write (single) */ + .bs_w_1 = _pci_mem_bs_w_1, + .bs_w_2 = _pci_mem_bs_w_2, + .bs_w_4 = _pci_mem_bs_w_4, - /* - * IXP425 processor does not have PCI I/O windows - */ + .bs_w_1_s = ixp425_pci_mem_bs_w_1, + .bs_w_2_s = ixp425_pci_mem_bs_w_2, + .bs_w_4_s = ixp425_pci_mem_bs_w_4, +#else /* read (single) */ - bs->bs_r_1 = _pci_io_bs_r_1; - bs->bs_r_2 = _pci_io_bs_r_2; - bs->bs_r_4 = _pci_io_bs_r_4; + .bs_r_1 = ixp425_pci_mem_bs_r_1, + .bs_r_2 = ixp425_pci_mem_bs_r_2, + .bs_r_4 = ixp425_pci_mem_bs_r_4, + .bs_r_1_s = ixp425_pci_mem_bs_r_1, + .bs_r_2_s = ixp425_pci_mem_bs_r_2, + .bs_r_4_s = ixp425_pci_mem_bs_r_4, /* write (single) */ - bs->bs_w_1 = _pci_io_bs_w_1; - bs->bs_w_2 = _pci_io_bs_w_2; - bs->bs_w_4 = _pci_io_bs_w_4; -} + .bs_w_1 = ixp425_pci_mem_bs_w_1, + .bs_w_2 = ixp425_pci_mem_bs_w_2, + .bs_w_4 = ixp425_pci_mem_bs_w_4, + .bs_w_1_s = ixp425_pci_mem_bs_w_1, + .bs_w_2_s = ixp425_pci_mem_bs_w_2, + .bs_w_4_s = ixp425_pci_mem_bs_w_4, +#endif +}; void ixp425_mem_bs_init(bus_space_tag_t bs, void *cookie) { - *bs = ixp425_pci_bs_tag_template; + *bs = ixp425_pci_mem_bs_tag_template; bs->bs_cookie = cookie; - - bs->bs_map = ixp425_pci_mem_bs_map; - bs->bs_unmap = ixp425_pci_mem_bs_unmap; - bs->bs_alloc = ixp425_pci_mem_bs_alloc; - bs->bs_free = ixp425_pci_mem_bs_free; - - /* read (single) */ - bs->bs_r_1 = ixp425_pci_mem_bs_r_1; - bs->bs_r_2 = ixp425_pci_mem_bs_r_2; - bs->bs_r_4 = ixp425_pci_mem_bs_r_4; - - /* write (single) */ - bs->bs_w_1 = ixp425_pci_mem_bs_w_1; - bs->bs_w_2 = ixp425_pci_mem_bs_w_2; - bs->bs_w_4 = ixp425_pci_mem_bs_w_4; } /* common routine */ @@ -243,56 +251,100 @@ } /* special I/O functions */ -#if 1 /* _pci_io_bs_{rw}_{124} */ -inline u_int8_t -_pci_io_bs_r_1(void *v, bus_space_handle_t ioh, bus_size_t off) +static __inline u_int32_t +_bs_r(void *v, bus_space_handle_t ioh, bus_size_t off, u_int32_t be) { - u_int32_t data, n, be; + u_int32_t data; - n = (ioh + off) % 4; - be = (0xf & ~(1U << n)) << NP_CBE_SHIFT; - CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3); CSR_WRITE_4(PCI_NP_CBE, be | COMMAND_NP_IO_READ); data = CSR_READ_4(PCI_NP_RDATA); if (CSR_READ_4(PCI_ISR) & ISR_PFE) CSR_WRITE_4(PCI_ISR, ISR_PFE); + return data; +} + +static u_int8_t +_pci_io_bs_r_1(void *v, bus_space_handle_t ioh, bus_size_t off) +{ + u_int32_t data, n, be; + + n = (ioh + off) % 4; + be = (0xf & ~(1U << n)) << NP_CBE_SHIFT; + data = _bs_r(v, ioh, off, be); + return data >> (8 * n); } -inline u_int16_t +static u_int16_t _pci_io_bs_r_2(void *v, bus_space_handle_t ioh, bus_size_t off) { u_int32_t data, n, be; n = (ioh + off) % 4; be = (0xf & ~((1U << n) | (1U << (n + 1)))) << NP_CBE_SHIFT; + data = _bs_r(v, ioh, off, be); + + return data >> (8 * n); +} + +static u_int32_t +_pci_io_bs_r_4(void *v, bus_space_handle_t ioh, bus_size_t off) +{ + u_int32_t data; + + data = _bs_r(v, ioh, off, 0); + return le32toh(data); +} + +#ifdef __ARMEB__ +static u_int8_t +_pci_io_bs_r_1_s(void *v, bus_space_handle_t ioh, bus_size_t off) +{ + u_int32_t data, n, be; - CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3); - CSR_WRITE_4(PCI_NP_CBE, be | COMMAND_NP_IO_READ); - data = CSR_READ_4(PCI_NP_RDATA); - if (CSR_READ_4(PCI_ISR) & ISR_PFE) - CSR_WRITE_4(PCI_ISR, ISR_PFE); + n = (ioh + off) % 4; + be = (0xf & ~(1U << n)) << NP_CBE_SHIFT; + data = _bs_r(v, ioh, off, be); + + return data >> (8 * n); +} + +static u_int16_t +_pci_io_bs_r_2_s(void *v, bus_space_handle_t ioh, bus_size_t off) +{ + u_int32_t data, n, be; + + n = (ioh + off) % 4; + be = (0xf & ~((1U << n) | (1U << (n + 1)))) << NP_CBE_SHIFT; + data = _bs_r(v, ioh, off, be); return data >> (8 * n); } -inline u_int32_t -_pci_io_bs_r_4(void *v, bus_space_handle_t ioh, bus_size_t off) +static u_int32_t +_pci_io_bs_r_4_s(void *v, bus_space_handle_t ioh, bus_size_t off) { u_int32_t data; + data = _bs_r(v, ioh, off, 0); + return data; +} +#endif /* __ARMEB__ */ + +static __inline void +_bs_w(void *v, bus_space_handle_t ioh, bus_size_t off, + u_int32_t be, u_int32_t data) +{ CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3); - CSR_WRITE_4(PCI_NP_CBE, COMMAND_NP_IO_READ); - data = CSR_READ_4(PCI_NP_RDATA); + CSR_WRITE_4(PCI_NP_CBE, be | COMMAND_NP_IO_WRITE); + CSR_WRITE_4(PCI_NP_WDATA, data); if (CSR_READ_4(PCI_ISR) & ISR_PFE) CSR_WRITE_4(PCI_ISR, ISR_PFE); - - return data; } -inline void +static void _pci_io_bs_w_1(void *v, bus_space_handle_t ioh, bus_size_t off, u_int8_t val) { @@ -301,15 +353,10 @@ n = (ioh + off) % 4; be = (0xf & ~(1U << n)) << NP_CBE_SHIFT; data = val << (8 * n); - - CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3); - CSR_WRITE_4(PCI_NP_CBE, be | COMMAND_NP_IO_WRITE); - CSR_WRITE_4(PCI_NP_WDATA, data); - if (CSR_READ_4(PCI_ISR) & ISR_PFE) - CSR_WRITE_4(PCI_ISR, ISR_PFE); + _bs_w(v, ioh, off, be, data); } -inline void +static void _pci_io_bs_w_2(void *v, bus_space_handle_t ioh, bus_size_t off, u_int16_t val) { @@ -318,25 +365,48 @@ n = (ioh + off) % 4; be = (0xf & ~((1U << n) | (1U << (n + 1)))) << NP_CBE_SHIFT; data = val << (8 * n); - - CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3); - CSR_WRITE_4(PCI_NP_CBE, be | COMMAND_NP_IO_WRITE); - CSR_WRITE_4(PCI_NP_WDATA, data); - if (CSR_READ_4(PCI_ISR) & ISR_PFE) - CSR_WRITE_4(PCI_ISR, ISR_PFE); + _bs_w(v, ioh, off, be, data); } -inline void +static void _pci_io_bs_w_4(void *v, bus_space_handle_t ioh, bus_size_t off, u_int32_t val) { - CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3); - CSR_WRITE_4(PCI_NP_CBE, COMMAND_NP_IO_WRITE); - CSR_WRITE_4(PCI_NP_WDATA, val); - if (CSR_READ_4(PCI_ISR) & ISR_PFE) - CSR_WRITE_4(PCI_ISR, ISR_PFE); + _bs_w(v, ioh, off, 0, htole32(val)); +} + +#ifdef __ARMEB__ +static void +_pci_io_bs_w_1_s(void *v, bus_space_handle_t ioh, bus_size_t off, + u_int8_t val) +{ + u_int32_t data, n, be; + + n = (ioh + off) % 4; + be = (0xf & ~(1U << n)) << NP_CBE_SHIFT; + data = val << (8 * n); + _bs_w(v, ioh, off, be, data); +} + +static void +_pci_io_bs_w_2_s(void *v, bus_space_handle_t ioh, bus_size_t off, + u_int16_t val) +{ + u_int32_t data, n, be; + + n = (ioh + off) % 4; + be = (0xf & ~((1U << n) | (1U << (n + 1)))) << NP_CBE_SHIFT; + data = val << (8 * n); + _bs_w(v, ioh, off, be, data); +} + +static void +_pci_io_bs_w_4_s(void *v, bus_space_handle_t ioh, bus_size_t off, + u_int32_t val) +{ + _bs_w(v, ioh, off, 0, val); } -#endif /* _pci_io_bs_{rw}_{124} */ +#endif /* __ARMEB__ */ /* mem bs */ int @@ -379,4 +449,48 @@ panic("ixp425_mem_bs_free(): not implemented\n"); } +#ifdef __ARMEB__ +static u_int8_t +_pci_mem_bs_r_1(void *v, bus_space_handle_t ioh, bus_size_t off) +{ + return ixp425_pci_mem_bs_r_1(v, ioh, off); +} + +static u_int16_t +_pci_mem_bs_r_2(void *v, bus_space_handle_t ioh, bus_size_t off) +{ + return ixp425_pci_mem_bs_r_2(v, ioh, off); +} + +static u_int32_t +_pci_mem_bs_r_4(void *v, bus_space_handle_t ioh, bus_size_t off) +{ + u_int32_t data; + + data = ixp425_pci_mem_bs_r_4(v, ioh, off); + return le32toh(data); +} + +static void +_pci_mem_bs_w_1(void *v, bus_space_handle_t ioh, bus_size_t off, + u_int8_t val) +{ + ixp425_pci_mem_bs_w_1(v, ioh, off, val); +} + +static void +_pci_mem_bs_w_2(void *v, bus_space_handle_t ioh, bus_size_t off, + u_int16_t val) +{ + ixp425_pci_mem_bs_w_2(v, ioh, off, val); +} + +static void +_pci_mem_bs_w_4(void *v, bus_space_handle_t ioh, bus_size_t off, + u_int32_t val) +{ + ixp425_pci_mem_bs_w_4(v, ioh, off, htole32(val)); +} +#endif /* __ARMEB__ */ + /* End of ixp425_pci_space.c */ ==== //depot/projects/arm/src/sys/arm/xscale/ixp425/ixp425_space.c#2 (text+ko) ==== @@ -64,73 +64,70 @@ struct bus_space ixp425_bs_tag = { /* cookie */ - (void *) 0, + .bs_cookie = (void *) 0, /* mapping/unmapping */ - ixp425_bs_map, - ixp425_bs_unmap, - ixp425_bs_subregion, + .bs_map = ixp425_bs_map, + .bs_unmap = ixp425_bs_unmap, + .bs_subregion = ixp425_bs_subregion, /* allocation/deallocation */ - ixp425_bs_alloc, - ixp425_bs_free, + .bs_alloc = ixp425_bs_alloc, + .bs_free = ixp425_bs_free, /* barrier */ - ixp425_bs_barrier, + .bs_barrier = ixp425_bs_barrier, /* read (single) */ - generic_bs_r_1, - generic_armv4_bs_r_2, - generic_bs_r_4, - NULL, + .bs_r_1 = generic_bs_r_1, + .bs_r_2 = generic_armv4_bs_r_2, + .bs_r_4 = generic_bs_r_4, + .bs_r_8 = NULL, /* read multiple */ - generic_bs_rm_1, - generic_armv4_bs_rm_2, - generic_bs_rm_4, - NULL, + .bs_rm_1 = generic_bs_rm_1, + .bs_rm_2 = generic_armv4_bs_rm_2, + .bs_rm_4 = generic_bs_rm_4, + .bs_rm_8 = NULL, /* read region */ - generic_bs_rr_1, - generic_armv4_bs_rr_2, - generic_bs_rr_4, - NULL, + .bs_rr_1 = generic_bs_rr_1, + .bs_rr_2 = generic_armv4_bs_rr_2, + .bs_rr_4 = generic_bs_rr_4, + .bs_rr_8 = NULL, /* write (single) */ - generic_bs_w_1, - generic_armv4_bs_w_2, - generic_bs_w_4, - NULL, + .bs_w_1 = generic_bs_w_1, + .bs_w_2 = generic_armv4_bs_w_2, + .bs_w_4 = generic_bs_w_4, + .bs_w_8 = NULL, /* write multiple */ - generic_bs_wm_1, - generic_armv4_bs_wm_2, - generic_bs_wm_4, - NULL, + .bs_wm_1 = generic_bs_wm_1, + .bs_wm_2 = generic_armv4_bs_wm_2, + .bs_wm_4 = generic_bs_wm_4, + .bs_wm_8 = NULL, /* write region */ - generic_bs_wr_1, - generic_armv4_bs_wr_2, - generic_bs_wr_4, - NULL, + .bs_wr_1 = generic_bs_wr_1, + .bs_wr_2 = generic_armv4_bs_wr_2, + .bs_wr_4 = generic_bs_wr_4, + .bs_wr_8 = NULL, /* set multiple */ - NULL, - NULL, - NULL, - NULL, + /* XXX not implemented */ /* set region */ - NULL, - generic_armv4_bs_sr_2, - generic_bs_sr_4, - NULL, + .bs_sr_1 = NULL, + .bs_sr_2 = generic_armv4_bs_sr_2, + .bs_sr_4 = generic_bs_sr_4, + .bs_sr_8 = NULL, /* copy */ - NULL, - generic_armv4_bs_c_2, - NULL, - NULL, + .bs_c_1 = NULL, + .bs_c_2 = generic_armv4_bs_c_2, + .bs_c_4 = NULL, + .bs_c_8 = NULL, }; int
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