Date: Tue, 30 Aug 2011 08:16:53 -0400 From: John Baldwin <jhb@freebsd.org> To: freebsd-hackers@freebsd.org Cc: hilfi alkaff <hilfialkaff@gmail.com> Subject: Re: pcie initialization with acpi Message-ID: <201108300816.54198.jhb@freebsd.org> In-Reply-To: <CAGKjdpj8h7z2uUkAJLcpPjiHhD-HUfT71y=QgeBgO7zSRT-jZg@mail.gmail.com> References: <CAGKjdpj8h7z2uUkAJLcpPjiHhD-HUfT71y=QgeBgO7zSRT-jZg@mail.gmail.com>
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On Friday, August 26, 2011 9:02:34 pm hilfi alkaff wrote: > Hi, > > I would like to learn more of the above matter. After the MCFG table gets > discovered with acpi, what does the address given by the > ACPI_MCFG_ALLOCATION* tells you? Does that tell you the address of the > extended configuration space of pci express? No, it tells you about a memory-mapped region you can use for all PCI config access. The region is defined to give the full config space access per device (so the lower N bits in the address are used to address a given config register within a single device). This macro details how the address mapping works: #define PCIE_VADDR(base, reg, bus, slot, func) \ ((base) + \ ((((bus) & 0xff) << 20) | \ (((slot) & 0x1f) << 15) | \ (((func) & 0x7) << 12) | \ ((reg) & 0xfff))) So the lower 12 bits select the register and the next 16 bits specify the device's bus/slot/function. > Also, is BSD distinguishing between reading from pcie config & pci config? > Because there's this pciereg_cfgread() function that seem to do that. I > thought pcie config space is just at the offset of 0x100 from pci config > space? BSD only distinguishes in that it refuses to access registers above 0x100 if MCFG is not in use on x86. If MCFG is in use, it is used for all config access (both "standard" and "extended"). See this routine for an example: /* * Write configuration space register */ void pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes) { if (cfgmech == CFGMECH_PCIE && (bus >= pcie_minbus && bus <= pcie_maxbus) && (bus != 0 || !(1 << slot & pcie_badslots))) pciereg_cfgwrite(bus, slot, func, reg, data, bytes); else pcireg_cfgwrite(bus, slot, func, reg, data, bytes); } If the device is on a bus managed by MCFG (pcie_minbus <= bus <= pcie_maxbus) and it's not subject to a quirk we use for some broken HT chipsets (the pcie_badslots that lists known "broken" slots on bus 0 for the broken chipsets), then MCFG is used for all config access. -- John Baldwin
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