Date: Sun, 27 Jan 2008 22:50:44 GMT From: Warner Losh <imp@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 134254 for review Message-ID: <200801272250.m0RMoi8M059645@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=134254 Change 134254 by imp@imp_paco-paco on 2008/01/27 22:50:12 Cut over to using mips2-based interrupt handling stuff exclusively rather than the mixed mips2 and jmips which couldn't have worked. Affected files ... .. //depot/projects/mips2-jnpr/src/sys/conf/files.mips#11 edit .. //depot/projects/mips2-jnpr/src/sys/mips/mips/clock.c#5 edit .. //depot/projects/mips2-jnpr/src/sys/mips/mips/exception.S#8 edit .. //depot/projects/mips2-jnpr/src/sys/mips/mips/interrupt.c#6 edit .. //depot/projects/mips2-jnpr/src/sys/mips/mips/intr_machdep.c#2 edit .. //depot/projects/mips2-jnpr/src/sys/mips/mips/vm_machdep.c#11 edit Differences ... ==== //depot/projects/mips2-jnpr/src/sys/conf/files.mips#11 (text+ko) ==== @@ -46,7 +46,7 @@ mips/mips/elf_machdep.c standard mips/mips/exception.S standard mips/mips/gdb_machdep.c standard -mips/mips/interrupt.c standard +#mips/mips/interrupt.c standard mips/mips/mainbus.c standard mips/mips/pmap.c standard mips/mips/trap.c standard ==== //depot/projects/mips2-jnpr/src/sys/mips/mips/clock.c#5 (text+ko) ==== @@ -183,7 +183,7 @@ * Registers or an on-chip external clock. Set the appropirate * bit-number in idle_mask */ - idle_mask |= CR_INT_CLOCK; +// idle_mask |= CR_INT_CLOCK; /* * The counter register acts like timer which is incremented as ==== //depot/projects/mips2-jnpr/src/sys/mips/mips/exception.S#8 (text+ko) ==== @@ -565,7 +565,7 @@ */ la gp, _C_LABEL(_gp) addu a0, sp, STAND_ARG_SIZE - la k0, _C_LABEL(mips_interrupt) + la k0, _C_LABEL(cpu_intr) jalr k0 sw a3, STAND_RA_OFFSET + KERN_REG_SIZE(sp) /* @@ -649,7 +649,7 @@ /* * Call the interrupt handler. */ - la k0, _C_LABEL(mips_interrupt) + la k0, _C_LABEL(cpu_intr) jalr k0 sw a3, STAND_RA_OFFSET(sp) # for debugging ==== //depot/projects/mips2-jnpr/src/sys/mips/mips/interrupt.c#6 (text+ko) ==== @@ -1,4 +1,5 @@ /* $OpenBSD$ */ +#define DEBUG_INTR /*- * Copyright (c) 2001 Opsycon AB (www.opsycon.se / www.opsycon.com) @@ -150,15 +151,14 @@ pending = trapframe->cause & CR_IPEND & trapframe->sr; #ifdef DEBUG_INTR - printf("mips_interrupt(1): trapframe->cause = %x, pending = %x, ipending = %x, pcpl =%x, trapframe->ic = %x\n", - trapframe->cause, pending, ipending, pcpl, trapframe->ic); + printf("mips_interrupt(1): trapframe->cause = %x, pending = %x\n", + trapframe->cause, pending); #endif cause = pending; #ifdef DEBUG_INTR - printf("mips_interrupt(2): cause = %x, ipending = %x, pcpl = %x\n", - cause, ipending, pcpl); + printf("mips_interrupt(2): cause = %x\n", cause); #endif /* * generic clock intr handler to cover clockintr() and rtcintr(). @@ -204,9 +204,9 @@ * Reenable all non served hardware levels. */ #ifdef DEBUG_INTR - printf("3 sr = %x, cause = %x, spl = %x, ipending = %x\n", + printf("3 sr = %x, cause = %x, spl = %x\n", trapframe->sr, cause, - (trapframe->sr & ~cause & SR_INT_MASK) | SR_INT_ENAB, ipending); + (trapframe->sr & ~cause & SR_INT_MASK) | SR_INT_ENAB); #endif if (pending & SOFT_INT_MASK_0) { ==== //depot/projects/mips2-jnpr/src/sys/mips/mips/intr_machdep.c#2 (text+ko) ==== @@ -60,6 +60,7 @@ struct intr_event *event; int error; + printf("Establish HARD IRQ %d: filt %p handler %p arg %p\n", irq, filt, handler, arg); if (irq < 0 || irq > NHARD_IRQS) panic("%s called for unknown hard intr %d", __func__, irq); @@ -96,6 +97,7 @@ struct intr_event *event; int error; + printf("Establish SOFT IRQ %d: filt %p handler %p arg %p\n", irq, filt, handler, arg); if (irq < 0 || irq > NSOFT_IRQS) panic("%s called for unknown hard intr %d", __func__, irq); ==== //depot/projects/mips2-jnpr/src/sys/mips/mips/vm_machdep.c#11 (text+ko) ==== @@ -302,7 +302,8 @@ pcb2->pcb_context.val[1] = (register_t)td; pcb2->pcb_context.val[2] = (register_t)td->td_frame; /* Dont set IE bit in SR. sched lock release will take care of it */ - pcb2->pcb_context.val[11] = (ALL_INT_MASK & idle_mask); +/* idle_mask is jmips pcb2->pcb_context.val[11] = (ALL_INT_MASK & idle_mask); */ + pcb2->pcb_context.val[11] = 0; /* * FREEBSD_DEVELOPERS_FIXME: @@ -346,7 +347,8 @@ tf->a0 = (register_t)arg; tf->sr = SR_KSU_USER | SR_EXL; - tf->sr |= (ALL_INT_MASK & idle_mask) | SR_INT_ENAB; +/* tf->sr |= (ALL_INT_MASK & idle_mask) | SR_INT_ENAB; */ + /**XXX the above may now be wrong -- mips2 implements this as panic */ /* * FREEBSD_DEVELOPERS_FIXME: * Setup any other CPU-Specific registers (Not MIPS Standard)
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