Date: Tue, 18 Oct 2005 11:54:37 -0400 (EDT) From: Andrew Gallatin <gallatin@cs.duke.edu> To: John Baldwin <jhb@freebsd.org> Cc: cvs-src@freebsd.org, src-committers@freebsd.org, David Xu <davidxu@freebsd.org>, cvs-all@freebsd.org Subject: Re: cvs commit: src/sys/amd64/amd64 cpu_switch.S machdep.c Message-ID: <17237.6845.390864.858367@grasshopper.cs.duke.edu> In-Reply-To: <200510181101.03956.jhb@freebsd.org> References: <200510172310.j9HNAVPL013057@repoman.freebsd.org> <20051018094402.A29138@grasshopper.cs.duke.edu> <200510181101.03956.jhb@freebsd.org>
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John Baldwin writes: > On Tuesday 18 October 2005 09:44 am, Andrew Gallatin wrote: > > David Xu [davidxu@FreeBSD.org] wrote: > > > davidxu 2005-10-17 23:10:31 UTC > > > > > > FreeBSD src repository > > > > > > Modified files: > > > sys/amd64/amd64 cpu_switch.S machdep.c > > > Log: > > > Micro optimization for context switch. Eliminate code for saving > > > gs.base and fs.base. We always update pcb.pcb_gsbase and pcb.pcb_fsbase > > > when user wants to set them, in context switch routine, we only need to > > > write them into registers, we never have to read them out from registers > > > when thread is switched away. Since rdmsr is a serialization instruction, > > > micro benchmark shows it is worthy to do. > > > > Nice. This reduces lmbench context switch latency by about 0.4us (7.2 > > -> 6.8us), and reduces TCP loopback latency by about 0.9us (36.1 -> > > 35.2) on my dual core 3800+ > > > > It is a shame we can't find a way to use the TSC as a timecounter on > > SMP systems. It seems that about 40% of the context switch time is > > spent just waiting for the PIO read of the ACPI-fast or i8254 to > > return. > > You can try it by just setting the kern.timecounter.smp_tsc=1 tunable on boot. Yes, that's how I get my figure of 3us for PIO read, and 3.8us for the rest of the context switch. But its not currently practical on most machines, since we don't sync the TSC between cpus, or do anything to account for drift. Drew
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