Date: Tue, 30 Oct 2012 06:29:17 +0000 (UTC) From: Juli Mallett <jmallett@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r242345 - head/sys/mips/cavium Message-ID: <201210300629.q9U6THoX033153@svn.freebsd.org>
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Author: jmallett Date: Tue Oct 30 06:29:17 2012 New Revision: 242345 URL: http://svn.freebsd.org/changeset/base/242345 Log: Remove oct_read64 and oct_write64 and use their equivalents from the Simple Executive, which are used everywhere else in the Octeon port. While here, remove other unused things from octeon_pcmap_regs.h. Modified: head/sys/mips/cavium/octeon_pcmap_regs.h head/sys/mips/cavium/uart_cpu_octeonusart.c Modified: head/sys/mips/cavium/octeon_pcmap_regs.h ============================================================================== --- head/sys/mips/cavium/octeon_pcmap_regs.h Tue Oct 30 06:19:46 2012 (r242344) +++ head/sys/mips/cavium/octeon_pcmap_regs.h Tue Oct 30 06:29:17 2012 (r242345) @@ -47,148 +47,14 @@ #define __OCTEON_PCMAP_REGS_H__ #ifndef LOCORE - -/* - * Utility inlines & macros - */ - -#if defined(__mips_n64) -#define oct_write64(a, v) (*(volatile uint64_t *)(a) = (uint64_t)(v)) - -#define OCT_READ(n, t) \ -static inline t oct_read ## n(uintptr_t a) \ -{ \ - volatile t *p = (volatile t *)a; \ - return (*p); \ -} - -OCT_READ(64, uint64_t); - -#elif defined(__mips_n32) || defined(__mips_o32) -#if defined(__mips_n32) -static inline void oct_write64 (uint64_t csr_addr, uint64_t val64) -{ - __asm __volatile ( - ".set push\n" - ".set mips64\n" - "sd %0, 0(%1)\n" - ".set pop\n" - : - : "r"(val64), "r"(csr_addr)); -} - -#define OCT_READ(n, t, insn) \ -static inline t oct_read ## n(uint64_t a) \ -{ \ - uint64_t tmp; \ - \ - __asm __volatile ( \ - ".set push\n" \ - ".set mips64\n" \ - insn "\t%0, 0(%1)\n" \ - ".set pop\n" \ - : "=r"(tmp) \ - : "r"(a)); \ - return ((t)tmp); \ -} - -OCT_READ(64, uint64_t, "ld"); -#else - -/* - * XXX - * Add o32 variants that load the address into a register and the result out - * of a register properly, and simply disable interrupts before and after and - * hope that we don't need to refill or modify the TLB to access the address. - * I'd be a lot happier if csr_addr were a physical address and we mapped it - * into XKPHYS here so that we could guarantee that interrupts were the only - * kind of exception we needed to worry about. - * - * Also, some of this inline assembly is needlessly verbose. Oh, well. - */ -static inline void oct_write64 (uint64_t csr_addr, uint64_t val64) -{ - uint32_t csr_addrh = csr_addr >> 32; - uint32_t csr_addrl = csr_addr; - uint32_t valh = val64 >> 32; - uint32_t vall = val64; - uint32_t tmp1; - uint32_t tmp2; - uint32_t tmp3; - register_t sr; - - sr = intr_disable(); - - __asm __volatile ( - ".set push\n" - ".set mips64\n" - ".set noreorder\n" - ".set noat\n" - "dsll %0, %3, 32\n" - "dsll %1, %5, 32\n" - "dsll %2, %4, 32\n" - "dsrl %2, %2, 32\n" - "or %0, %0, %2\n" - "dsll %2, %6, 32\n" - "dsrl %2, %2, 32\n" - "or %1, %1, %2\n" - "sd %0, 0(%1)\n" - ".set pop\n" - : "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3) - : "r" (valh), "r" (vall), "r" (csr_addrh), "r" (csr_addrl)); - - intr_restore(sr); -} - -static inline uint64_t oct_read64 (uint64_t csr_addr) -{ - uint32_t csr_addrh = csr_addr >> 32; - uint32_t csr_addrl = csr_addr; - uint32_t valh; - uint32_t vall; - register_t sr; - - sr = intr_disable(); - - __asm __volatile ( - ".set push\n" - ".set mips64\n" - ".set noreorder\n" - ".set noat\n" - "dsll %0, %2, 32\n" - "dsll %1, %3, 32\n" - "dsrl %1, %1, 32\n" - "or %0, %0, %1\n" - "ld %1, 0(%0)\n" - "dsrl %0, %1, 32\n" - "dsll %1, %1, 32\n" - "dsrl %1, %1, 32\n" - ".set pop\n" - : "=&r" (valh), "=&r" (vall) - : "r" (csr_addrh), "r" (csr_addrl)); - - intr_restore(sr); - - return ((uint64_t)valh << 32) | vall; -} -#endif - -#endif - /* * octeon_machdep.c * * Direct to Board Support level. */ -extern void octeon_reset(void); -extern void octeon_debug_symbol(void); -extern void octeon_ciu_reset(void); -extern int octeon_is_simulation(void); +void octeon_debug_symbol(void); +void octeon_ciu_reset(void); +int octeon_is_simulation(void); #endif /* LOCORE */ -/* - * Default FLASH device (physical) base address - */ -#define OCTEON_FLASH_BASE_ADDR (0x1d040000ull) - #endif /* !OCTEON_PCMAP_REGS_H__ */ Modified: head/sys/mips/cavium/uart_cpu_octeonusart.c ============================================================================== --- head/sys/mips/cavium/uart_cpu_octeonusart.c Tue Oct 30 06:19:46 2012 (r242344) +++ head/sys/mips/cavium/uart_cpu_octeonusart.c Tue Oct 30 06:29:17 2012 (r242345) @@ -58,56 +58,56 @@ static uint8_t ou_bs_r_1(void *t, bus_space_handle_t handle, bus_size_t offset) { - return (oct_read64(handle + offset)); + return (cvmx_read64_uint64(handle + offset)); } static uint16_t ou_bs_r_2(void *t, bus_space_handle_t handle, bus_size_t offset) { - return (oct_read64(handle + offset)); + return (cvmx_read64_uint64(handle + offset)); } static uint32_t ou_bs_r_4(void *t, bus_space_handle_t handle, bus_size_t offset) { - return (oct_read64(handle + offset)); + return (cvmx_read64_uint64(handle + offset)); } static uint64_t ou_bs_r_8(void *t, bus_space_handle_t handle, bus_size_t offset) { - return (oct_read64(handle + offset)); + return (cvmx_read64_uint64(handle + offset)); } static void ou_bs_w_1(void *t, bus_space_handle_t bsh, bus_size_t offset, uint8_t value) { - oct_write64(bsh + offset, value); + cvmx_write64_uint64(bsh + offset, value); } static void ou_bs_w_2(void *t, bus_space_handle_t bsh, bus_size_t offset, uint16_t value) { - oct_write64(bsh + offset, value); + cvmx_write64_uint64(bsh + offset, value); } static void ou_bs_w_4(void *t, bus_space_handle_t bsh, bus_size_t offset, uint32_t value) { - oct_write64(bsh + offset, value); + cvmx_write64_uint64(bsh + offset, value); } static void ou_bs_w_8(void *t, bus_space_handle_t bsh, bus_size_t offset, uint64_t value) { - oct_write64(bsh + offset, value); + cvmx_write64_uint64(bsh + offset, value); } struct bus_space octeon_uart_tag = {
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