Date: Sun, 05 Jun 2011 23:04:39 +0300 From: Andriy Gapon <avg@FreeBSD.org> To: Jung-uk Kim <jkim@FreeBSD.org> Cc: freebsd-hackers@FreeBSD.org Subject: Re: [RFC] Enabling invariant TSC timecounter on SMP Message-ID: <4DEBE157.8030201@FreeBSD.org> In-Reply-To: <201106031228.58113.jkim@FreeBSD.org> References: <201105241356.45543.jkim@FreeBSD.org> <201106011655.51233.jkim@FreeBSD.org> <4DE8794B.60100@FreeBSD.org> <201106031228.58113.jkim@FreeBSD.org>
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on 03/06/2011 19:28 Jung-uk Kim said the following: > Unlike Intel, AMD did not guarantee "all TSCs reset to zero with RESET > IPI" before Bulldozer[1]. In fact, I tried to measure deltas between > cores when I started hacking on it using some crude heuristics, > somewhat like the OpenSolaris hack[2]. Basically, a dual-core AMD > Family 10h processor showed noticeably larger deltas than *two* > dual-core Intel Woodcrest Xeons'. You are right. I haven't had any problems with my Athlon II system with forced smp_tsc, but testing shows that it has a measurable difference in TSC between cores. E.g. with the "tsc_check" code: cpus 0-1, min_write_time = 186, tdelta = 316 cpus 0-1, TSCs are considered to be OUT of sync > [1] I couldn't find any clues from their publicly available documents > whether they will implement (or need) additional mechanism for > multi-socket Bulldozer platforms. It only says something like "all > TSCs are synchronized with a clock source in north bridge". We will > see when AMD Valencia & Interlagos are available. :-) > [2] Unfortunately, there is no way to accurately measure it with > current generation hardware. Yeah, quite unfortunate. -- Andriy Gapon
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