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Date:      Tue, 23 Sep 2025 17:09:33 GMT
From:      Andrew Turner <andrew@FreeBSD.org>
To:        src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org
Subject:   git: f38792ffc2db - main - arm64/vmm: Clean up enabling guest timer access
Message-ID:  <202509231709.58NH9XaU077251@gitrepo.freebsd.org>

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The branch main has been updated by andrew:

URL: https://cgit.FreeBSD.org/src/commit/?id=f38792ffc2db67ca82026eb4861f37fe7ac7c38e

commit f38792ffc2db67ca82026eb4861f37fe7ac7c38e
Author:     Andrew Turner <andrew@FreeBSD.org>
AuthorDate: 2025-09-22 17:08:06 +0000
Commit:     Andrew Turner <andrew@FreeBSD.org>
CommitDate: 2025-09-23 17:08:36 +0000

    arm64/vmm: Clean up enabling guest timer access
    
    Clean up the name of CNTHCTL_EL2 field macros and expand to include
    more fields. This makes it easier to see which accesses are trapped or
    not trapped.
    
    While here set the register directly. We already set it in locore.S so
    there is no need to read that and modify it.
    
    Sponsored by:   Arm Ltd
    Differential Revision:  https://reviews.freebsd.org/D51817
---
 sys/arm64/arm64/locore.S       |  4 +--
 sys/arm64/include/hypervisor.h | 79 ++++++++++++++++++++++++++++++++++++------
 sys/arm64/vmm/io/vtimer.c      | 31 ++++++++++-------
 3 files changed, 88 insertions(+), 26 deletions(-)

diff --git a/sys/arm64/arm64/locore.S b/sys/arm64/arm64/locore.S
index 50a3eda846da..d35e334905a7 100644
--- a/sys/arm64/arm64/locore.S
+++ b/sys/arm64/arm64/locore.S
@@ -418,7 +418,7 @@ LENTRY(enter_kernel_el)
 
 	msr	SCTLR_EL12_REG, x2
 	mov	x2, xzr /* CPTR_EL2 is managed by vfp.c */
-	ldr	x3, =(CNTHCTL_E2H_EL1PCTEN | CNTHCTL_E2H_EL1PTEN)
+	ldr	x3, =(CNTHCTL_E2H_EL1PCTEN_NOTRAP | CNTHCTL_E2H_EL1PTEN_NOTRAP)
 	ldr	x5, =(PSR_DAIF | PSR_M_EL2h)
 	b	.Ldone_vhe
 
@@ -429,7 +429,7 @@ LENTRY(enter_kernel_el)
 	msr	vbar_el2, x2
 
 	ldr	x2, =(CPTR_RES1)
-	ldr	x3, =(CNTHCTL_EL1PCTEN | CNTHCTL_EL1PCEN)
+	ldr	x3, =(CNTHCTL_EL1PCTEN_NOTRAP | CNTHCTL_EL1PCEN_NOTRAP)
 	ldr	x5, =(PSR_DAIF | PSR_M_EL1h)
 
 .Ldone_vhe:
diff --git a/sys/arm64/include/hypervisor.h b/sys/arm64/include/hypervisor.h
index e3a880afbe9c..04e15b55b218 100644
--- a/sys/arm64/include/hypervisor.h
+++ b/sys/arm64/include/hypervisor.h
@@ -36,20 +36,77 @@
  */
 
 /* CNTHCTL_EL2 - Counter-timer Hypervisor Control register */
-#define	CNTHCTL_EVNTI_MASK	(0xf << 4) /* Bit to trigger event stream */
 /* Valid if HCR_EL2.E2H == 0 */
-#define	CNTHCTL_EL1PCTEN	(1 << 0) /* Allow physical counter access */
-#define	CNTHCTL_EL1PCEN		(1 << 1) /* Allow physical timer access */
+#define	CNTHCTL_EL1PCTEN_SHIFT		0
+#define	CNTHCTL_EL1PCTEN_MASK		(0x1ul << CNTHCTL_E2H_EL1PCTEN_SHIFT)
+#define	 CNTHCTL_EL1PCTEN_TRAP		(0x0ul << CNTHCTL_E2H_EL1PCTEN_SHIFT)
+#define	 CNTHCTL_EL1PCTEN_NOTRAP	(0x1ul << CNTHCTL_EL1PCTEN_SHIFT)
+#define	CNTHCTL_EL1PCEN_SHIFT		1
+#define	CNTHCTL_EL1PCEN_MASK		(0x1ul << CNTHCTL_EL1PCEN_SHIFT)
+#define	 CNTHCTL_EL1PCEN_TRAP		(0x0ul << CNTHCTL_EL1PCEN_SHIFT)
+#define	 CNTHCTL_EL1PCEN_NOTRAP		(0x1ul << CNTHCTL_EL1PCEN_SHIFT)
 /* Valid if HCR_EL2.E2H == 1 */
-#define	CNTHCTL_E2H_EL0PCTEN	(1 << 0) /* Allow EL0 physical counter access */
-#define	CNTHCTL_E2H_EL0VCTEN	(1 << 1) /* Allow EL0 virtual counter access */
-#define	CNTHCTL_E2H_EL0VTEN	(1 << 8)
-#define	CNTHCTL_E2H_EL0PTEN	(1 << 9)
-#define	CNTHCTL_E2H_EL1PCTEN	(1 << 10) /* Allow physical counter access */
-#define	CNTHCTL_E2H_EL1PTEN	(1 << 11) /* Allow physical timer access */
+#define	CNTHCTL_E2H_EL0PCTEN_SHIFT	0
+#define	CNTHCTL_E2H_EL0PCTEN_MASK	(0x1ul << CNTHCTL_E2H_EL0PCTEN_SHIFT)
+#define	 CNTHCTL_E2H_EL0PCTEN_TRAP	(0x0ul << CNTHCTL_E2H_EL0PCTEN_SHIFT)
+#define	 CNTHCTL_E2H_EL0PCTEN_NOTRAP	(0x1ul << CNTHCTL_E2H_EL0PCTEN_SHIFT)
+#define	CNTHCTL_E2H_EL0VCTEN_SHIFT	1
+#define	CNTHCTL_E2H_EL0VCTEN_MASK	(0x1ul << CNTHCTL_E2H_EL0VCTEN_SHIFT)
+#define	 CNTHCTL_E2H_EL0VCTEN_TRAP	(0x0ul << CNTHCTL_E2H_EL0VCTEN_SHIFT)
+#define	 CNTHCTL_E2H_EL0VCTEN_NOTRAP	(0x1ul << CNTHCTL_E2H_EL0VCTEN_SHIFT)
+#define	CNTHCTL_E2H_EL0VTEN_SHIFT	8
+#define	CNTHCTL_E2H_EL0VTEN_MASK	(0x1ul << CNTHCTL_E2H_EL0VTEN_SHIFT)
+#define	 CNTHCTL_E2H_EL0VTEN_TRAP	(0x0ul << CNTHCTL_E2H_EL0VTEN_SHIFT)
+#define	 CNTHCTL_E2H_EL0VTEN_NOTRAP	(0x1ul << CNTHCTL_E2H_EL0VTEN_SHIFT)
+#define	CNTHCTL_E2H_EL0PTEN_SHIFT	9
+#define	CNTHCTL_E2H_EL0PTEN_MASK	(0x1ul << CNTHCTL_E2H_EL0PTEN_SHIFT)
+#define	 CNTHCTL_E2H_EL0PTEN_TRAP	(0x0ul << CNTHCTL_E2H_EL0PTEN_SHIFT)
+#define	 CNTHCTL_E2H_EL0PTEN_NOTRAP	(0x1ul << CNTHCTL_E2H_EL0PTEN_SHIFT)
+#define	CNTHCTL_E2H_EL1PCTEN_SHIFT	10
+#define	CNTHCTL_E2H_EL1PCTEN_MASK	(0x1ul << CNTHCTL_E2H_EL1PCTEN_SHIFT)
+#define	 CNTHCTL_E2H_EL1PCTEN_TRAP	(0x0ul << CNTHCTL_E2H_EL1PCTEN_SHIFT)
+#define	 CNTHCTL_E2H_EL1PCTEN_NOTRAP	(0x1ul << CNTHCTL_E2H_EL1PCTEN_SHIFT)
+#define	CNTHCTL_E2H_EL1PTEN_SHIFT	11
+#define	CNTHCTL_E2H_EL1PTEN_MASK	(0x1ul << CNTHCTL_E2H_EL1PTEN_SHIFT)
+#define	 CNTHCTL_E2H_EL1PTEN_TRAP	(0x0ul << CNTHCTL_E2H_EL1PTEN_SHIFT)
+#define	 CNTHCTL_E2H_EL1PTEN_NOTRAP	(0x1ul << CNTHCTL_E2H_EL1PTEN_SHIFT)
 /* Unconditionally valid */
-#define	CNTHCTL_EVNTDIR		(1 << 3) /* Control transition trigger bit */
-#define	CNTHCTL_EVNTEN		(1 << 2) /* Enable event stream */
+#define	CNTHCTL_EVNTEN_SHIFT		2
+#define	CNTHCTL_EVNTEN_MASK		(0x1ul << CNTHCTL_EVNTEN_SHIFT)
+#define	 CNTHCTL_EVNTEN_DIS		(0x0ul << CNTHCTL_EVNTEN_SHIFT)
+#define	 CNTHCTL_EVNTEN_EN		(0x1ul << CNTHCTL_EVNTEN_SHIFT)
+#define	CNTHCTL_EVNTDIR_SHIFT		3
+#define	CNTHCTL_EVNTDIR_MASK		(0x1ul << CNTHCTL_EVNTDIR_SHIFT)
+#define	 CNTHCTL_EVNTDIR_HIGH		(0x0ul << CNTHCTL_EVNTDIR_SHIFT)
+#define	 CNTHCTL_EVNTDIR_LOW		(0x1ul << CNTHCTL_EVNTDIR_SHIFT)
+#define	CNTHCTL_EVNTI_SHIFT		4
+#define	CNTHCTL_EVNTI_MASK		(0xful << CNTHCTL_EVNTI_SHIFT)
+#define	CNTHCTL_ECV_SHIFT		12
+#define	CNTHCTL_ECV_MASK		(0x1ul << CNTHCTL_ECV_SHIFT)
+#define	 CNTHCTL_ECV_DIS		(0x0ul << CNTHCTL_ECV_SHIFT)
+#define	 CNTHCTL_ECV_EN			(0x1ul << CNTHCTL_ECV_SHIFT)
+#define	CNTHCTL_EL1TVT_SHIFT		13
+#define	CNTHCTL_EL1TVT_MASK		(0x1ul << CNTHCTL_EL1TVT_SHIFT)
+#define	 CNTHCTL_EL1TVT_NOTRAP		(0x0ul << CNTHCTL_EL1TVT_SHIFT)
+#define	 CNTHCTL_EL1TVT_TRAP		(0x1ul << CNTHCTL_EL1TVT_SHIFT)
+#define	CNTHCTL_EL1TVCT_SHIFT		14
+#define	CNTHCTL_EL1TVCT_MASK		(0x1ul << CNTHCTL_EL1TVCT_SHIFT)
+#define	 CNTHCTL_EL1TVCT_NOTRAP		(0x0ul << CNTHCTL_EL1TVCT_SHIFT)
+#define	 CNTHCTL_EL1TVCT_TRAP		(0x1ul << CNTHCTL_EL1TVCT_SHIFT)
+#define	CNTHCTL_EL1NVPCT_SHIFT		15
+#define	CNTHCTL_EL1NVPCT_MASK		(0x1ul << CNTHCTL_EL1NVPCT_SHIFT)
+#define	 CNTHCTL_EL1NVPCT_NOTRAP	(0x0ul << CNTHCTL_EL1NVPCT_SHIFT)
+#define	 CNTHCTL_EL1NVPCT_TRAP		(0x1ul << CNTHCTL_EL1NVPCT_SHIFT)
+#define	CNTHCTL_EL1NVVCT_SHIFT		16
+#define	CNTHCTL_EL1NVVCT_MASK		(0x1ul << CNTHCTL_EL1NVVCT_SHIFT)
+#define	 CNTHCTL_EL1NVVCT_NOTRAP	(0x0ul << CNTHCTL_EL1NVVCT_SHIFT)
+#define	 CNTHCTL_EL1NVVCT_TRAP		(0x1ul << CNTHCTL_EL1NVVCT_SHIFT)
+#define	CNTHCTL_EVNTIS_SHIFT		17
+#define	CNTHCTL_EVNTIS_MASK		(0x1ul << CNTHCTL_EVNTIS_SHIFT)
+#define	CNTHCTL_CNTVMASK_SHIFT		18
+#define	CNTHCTL_CNTVMASK_MASK		(0x1ul << CNTHCTL_CNTVMASK_SHIFT)
+#define	CNTHCTL_CNTPMASK_SHIFT		19
+#define	CNTHCTL_CNTPMASK_MASK		(0x1ul << CNTHCTL_CNTPMASK_SHIFT)
 
 /* CNTPOFF_EL2 - Counter-timer Physical Offset Register */
 #define	CNTPOFF_EL2_REG			MRS_REG_ALT_NAME(CNTPOFF_EL2)
diff --git a/sys/arm64/vmm/io/vtimer.c b/sys/arm64/vmm/io/vtimer.c
index f59d7ebc1ad4..51b21110d42c 100644
--- a/sys/arm64/vmm/io/vtimer.c
+++ b/sys/arm64/vmm/io/vtimer.c
@@ -137,33 +137,38 @@ vtimer_vminit(struct hyp *hyp)
 	if (in_vhe()) {
 		/*
 		 * CNTHCTL_E2H_EL0PCTEN: trap EL0 access to CNTP{CT,CTSS}_EL0
-		 * CNTHCTL_E2H_EL1VCTEN: don't trap EL0 access to
-		 *                       CNTV{CT,CTSS}_EL0
+		 * CNTHCTL_E2H_EL0VCTEN: don't trap EL0 access to
+		 *                      CNTV{CT,CTXX}_EL0
 		 * CNTHCTL_E2H_EL0VTEN: don't trap EL0 access to
 		 *                      CNTV_{CTL,CVAL,TVAL}_EL0
 		 * CNTHCTL_E2H_EL0PTEN: trap EL0 access to
 		 *                      CNTP_{CTL,CVAL,TVAL}_EL0
-		 * CNTHCTL_E2H_EL1PCEN: trap EL1 access to
-		                        CNTP_{CTL,CVAL,TVAL}_EL0
 		 * CNTHCTL_E2H_EL1PCTEN: trap access to CNTPCT_EL0
+		 * CNTHCTL_E2H_EL1PTEN: trap access to
+		 *                      CNTP_{CTL,CVAL,TVAL}_EL0
+		 * CNTHCTL_E2H_EL1VCTEN: don't trap EL0 access to
+		 *                       CNTV{CT,CTSS}_EL0
+		 * CNTHCTL_E2H_EL1PCEN: trap EL1 access to
+		 *                      CNTP_{CTL,CVAL,TVAL}_EL0
 		 *
 		 * TODO: Don't trap when FEAT_ECV is present
 		 */
-		hyp->vtimer.cnthctl_el2 &= ~CNTHCTL_E2H_EL0PCTEN;
-		hyp->vtimer.cnthctl_el2 |= CNTHCTL_E2H_EL0VCTEN;
-		hyp->vtimer.cnthctl_el2 |= CNTHCTL_E2H_EL0VTEN;
-		hyp->vtimer.cnthctl_el2 &= ~CNTHCTL_E2H_EL0PTEN;
-
-		hyp->vtimer.cnthctl_el2 &= ~CNTHCTL_E2H_EL1PTEN;
-		hyp->vtimer.cnthctl_el2 &= ~CNTHCTL_E2H_EL1PCTEN;
+		hyp->vtimer.cnthctl_el2 =
+		    CNTHCTL_E2H_EL0PCTEN_TRAP |
+		    CNTHCTL_E2H_EL0VCTEN_NOTRAP |
+		    CNTHCTL_E2H_EL0VTEN_NOTRAP |
+		    CNTHCTL_E2H_EL0PTEN_TRAP |
+		    CNTHCTL_E2H_EL1PCTEN_TRAP |
+		    CNTHCTL_E2H_EL1PTEN_TRAP;
 	} else {
 		/*
 		 * CNTHCTL_EL1PCEN: trap access to CNTP_{CTL, CVAL, TVAL}_EL0
 		 *                  from EL1
 		 * CNTHCTL_EL1PCTEN: trap access to CNTPCT_EL0
 		 */
-		hyp->vtimer.cnthctl_el2 &= ~CNTHCTL_EL1PCEN;
-		hyp->vtimer.cnthctl_el2 &= ~CNTHCTL_EL1PCTEN;
+		hyp->vtimer.cnthctl_el2 =
+		    CNTHCTL_EL1PCTEN_TRAP |
+		    CNTHCTL_EL1PCEN_TRAP;
 	}
 
 	now = READ_SPECIALREG(cntpct_el0);



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