Date: Mon, 4 Jul 2022 18:09:21 GMT From: Alexander Motin <mav@FreeBSD.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-branches@FreeBSD.org Subject: git: e7b63a7c6d62 - stable/13 - hwpmc: Update Intel's programmable counters restrictions. Message-ID: <202207041809.264I9LVA064378@gitrepo.freebsd.org>
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The branch stable/13 has been updated by mav: URL: https://cgit.FreeBSD.org/src/commit/?id=e7b63a7c6d62b4628373577792f842d71611b53a commit e7b63a7c6d62b4628373577792f842d71611b53a Author: Alexander Motin <mav@FreeBSD.org> AuthorDate: 2022-05-31 02:51:00 +0000 Commit: Alexander Motin <mav@FreeBSD.org> CommitDate: 2022-07-04 17:48:09 +0000 hwpmc: Update Intel's programmable counters restrictions. Primarily remove unneeded restrictions from later CPUs. MFC after: 1 month (cherry picked from commit ae57fbc7ec65fcc75575a55c911e0da32ea9c20d) --- sys/dev/hwpmc/hwpmc_core.c | 101 ++++++++++++++++++++++++--------------------- 1 file changed, 54 insertions(+), 47 deletions(-) diff --git a/sys/dev/hwpmc/hwpmc_core.c b/sys/dev/hwpmc/hwpmc_core.c index 7d359e732291..2ec6ac794f62 100644 --- a/sys/dev/hwpmc/hwpmc_core.c +++ b/sys/dev/hwpmc/hwpmc_core.c @@ -615,20 +615,22 @@ iap_event_corei7_ok_on_counter(uint8_t evsel, int ri) uint32_t mask; switch (evsel) { - /* - * Events valid only on counter 0, 1. - */ - case 0x40: - case 0x41: - case 0x42: - case 0x43: - case 0x51: - case 0x63: - mask = 0x3; + /* Events valid only on counter 0, 1. */ + case 0x40: + case 0x41: + case 0x42: + case 0x43: + case 0x4C: + case 0x4E: + case 0x51: + case 0x52: + case 0x53: + case 0x63: + mask = 0x3; break; - - default: - mask = ~0; /* Any row index is ok. */ + /* Any row index is ok. */ + default: + mask = ~0; } return (mask & (1 << ri)); @@ -640,26 +642,23 @@ iap_event_westmere_ok_on_counter(uint8_t evsel, int ri) uint32_t mask; switch (evsel) { - /* - * Events valid only on counter 0. - */ - case 0x60: - case 0xB3: + /* Events valid only on counter 0. */ + case 0x60: + case 0xB3: mask = 0x1; break; - /* - * Events valid only on counter 0, 1. - */ - case 0x4C: - case 0x4E: - case 0x51: - case 0x63: + /* Events valid only on counter 0, 1. */ + case 0x4C: + case 0x4E: + case 0x51: + case 0x52: + case 0x63: mask = 0x3; break; - + /* Any row index is ok. */ default: - mask = ~0; /* Any row index is ok. */ + mask = ~0; } return (mask & (1 << ri)); @@ -671,34 +670,35 @@ iap_event_sb_sbx_ib_ibx_ok_on_counter(uint8_t evsel, int ri) uint32_t mask; switch (evsel) { - /* Events valid only on counter 0. */ - case 0xB7: + /* Events valid only on counter 0. */ + case 0xB7: mask = 0x1; break; - /* Events valid only on counter 1. */ + /* Events valid only on counter 1. */ case 0xC0: mask = 0x2; break; - /* Events valid only on counter 2. */ + /* Events valid only on counter 2. */ case 0x48: case 0xA2: case 0xA3: mask = 0x4; break; - /* Events valid only on counter 3. */ + /* Events valid only on counter 3. */ case 0xBB: case 0xCD: mask = 0x8; break; + /* Any row index is ok. */ default: - mask = ~0; /* Any row index is ok. */ + mask = ~0; } return (mask & (1 << ri)); } static int -iap_event_ok_on_counter(uint8_t evsel, int ri) +iap_event_core_ok_on_counter(uint8_t evsel, int ri) { uint32_t mask; @@ -752,34 +752,41 @@ iap_allocate_pmc(int cpu, int ri, struct pmc *pm, ev = IAP_EVSEL_GET(iap->pm_iap_config); switch (core_cputype) { + case PMC_CPU_INTEL_CORE: + case PMC_CPU_INTEL_CORE2: + case PMC_CPU_INTEL_CORE2EXTREME: + if (iap_event_core_ok_on_counter(ev, ri) == 0) + return (EINVAL); case PMC_CPU_INTEL_COREI7: case PMC_CPU_INTEL_NEHALEM_EX: if (iap_event_corei7_ok_on_counter(ev, ri) == 0) return (EINVAL); break; - case PMC_CPU_INTEL_SKYLAKE: - case PMC_CPU_INTEL_SKYLAKE_XEON: - case PMC_CPU_INTEL_ICELAKE: - case PMC_CPU_INTEL_ICELAKE_XEON: - case PMC_CPU_INTEL_BROADWELL: - case PMC_CPU_INTEL_BROADWELL_XEON: + case PMC_CPU_INTEL_WESTMERE: + case PMC_CPU_INTEL_WESTMERE_EX: + if (iap_event_westmere_ok_on_counter(ev, ri) == 0) + return (EINVAL); + break; case PMC_CPU_INTEL_SANDYBRIDGE: case PMC_CPU_INTEL_SANDYBRIDGE_XEON: case PMC_CPU_INTEL_IVYBRIDGE: case PMC_CPU_INTEL_IVYBRIDGE_XEON: case PMC_CPU_INTEL_HASWELL: case PMC_CPU_INTEL_HASWELL_XEON: + case PMC_CPU_INTEL_BROADWELL: + case PMC_CPU_INTEL_BROADWELL_XEON: if (iap_event_sb_sbx_ib_ibx_ok_on_counter(ev, ri) == 0) return (EINVAL); break; - case PMC_CPU_INTEL_WESTMERE: - case PMC_CPU_INTEL_WESTMERE_EX: - if (iap_event_westmere_ok_on_counter(ev, ri) == 0) - return (EINVAL); - break; + case PMC_CPU_INTEL_ATOM: + case PMC_CPU_INTEL_ATOM_SILVERMONT: + case PMC_CPU_INTEL_ATOM_GOLDMONT: + case PMC_CPU_INTEL_SKYLAKE: + case PMC_CPU_INTEL_SKYLAKE_XEON: + case PMC_CPU_INTEL_ICELAKE: + case PMC_CPU_INTEL_ICELAKE_XEON: default: - if (iap_event_ok_on_counter(ev, ri) == 0) - return (EINVAL); + break; } pm->pm_md.pm_iap.pm_iap_evsel = iap->pm_iap_config;
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