Date: Mon, 4 Jul 2022 18:09:22 GMT From: Alexander Motin <mav@FreeBSD.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-branches@FreeBSD.org Subject: git: b8ef2ca9eae9 - stable/13 - hwpmc: Add basic Intel Alderlake CPUs support. Message-ID: <202207041809.264I9MKe064402@gitrepo.freebsd.org>
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The branch stable/13 has been updated by mav: URL: https://cgit.FreeBSD.org/src/commit/?id=b8ef2ca9eae9fe8167708413f142d02aa0f02255 commit b8ef2ca9eae9fe8167708413f142d02aa0f02255 Author: Alexander Motin <mav@FreeBSD.org> AuthorDate: 2022-05-31 03:17:37 +0000 Commit: Alexander Motin <mav@FreeBSD.org> CommitDate: 2022-07-04 17:48:09 +0000 hwpmc: Add basic Intel Alderlake CPUs support. The PMC subsystem is not designed for non-uniform CPU capabilities (P/E-cores are different), but at least several working architectural events like cpu_clk_unhalted.thread_p should be better than nothing. MFC after: 1 month (cherry picked from commit fe109d3113166c8e3b8557f0569c4e5a3597ac93) --- sys/dev/hwpmc/hwpmc_core.c | 1 + sys/dev/hwpmc/hwpmc_intel.c | 107 +++++++++++--------------------------------- sys/sys/pmc.h | 1 + 3 files changed, 29 insertions(+), 80 deletions(-) diff --git a/sys/dev/hwpmc/hwpmc_core.c b/sys/dev/hwpmc/hwpmc_core.c index 2ec6ac794f62..41896ffb7b8e 100644 --- a/sys/dev/hwpmc/hwpmc_core.c +++ b/sys/dev/hwpmc/hwpmc_core.c @@ -785,6 +785,7 @@ iap_allocate_pmc(int cpu, int ri, struct pmc *pm, case PMC_CPU_INTEL_SKYLAKE_XEON: case PMC_CPU_INTEL_ICELAKE: case PMC_CPU_INTEL_ICELAKE_XEON: + case PMC_CPU_INTEL_ALDERLAKE: default: break; } diff --git a/sys/dev/hwpmc/hwpmc_intel.c b/sys/dev/hwpmc/hwpmc_intel.c index 2d8377e1a838..f59b7b41ece9 100644 --- a/sys/dev/hwpmc/hwpmc_intel.c +++ b/sys/dev/hwpmc/hwpmc_intel.c @@ -163,6 +163,27 @@ pmc_intel_initialize(void) cputype = PMC_CPU_INTEL_IVYBRIDGE_XEON; nclasses = 3; break; + case 0x3D: + case 0x47: + cputype = PMC_CPU_INTEL_BROADWELL; + nclasses = 3; + break; + case 0x4f: + case 0x56: + cputype = PMC_CPU_INTEL_BROADWELL_XEON; + nclasses = 3; + break; + case 0x3C: /* Per Intel document 325462-045US 01/2013. */ + case 0x45: /* Per Intel document 325462-045US 09/2014. */ + cputype = PMC_CPU_INTEL_HASWELL; + nclasses = 3; + break; + case 0x3F: /* Per Intel document 325462-045US 09/2014. */ + case 0x46: /* Per Intel document 325462-045US 09/2014. */ + /* Should 46 be XEON. probably its own? */ + cputype = PMC_CPU_INTEL_HASWELL_XEON; + nclasses = 3; + break; /* Skylake */ case 0x4e: case 0x5e: @@ -195,25 +216,9 @@ pmc_intel_initialize(void) cputype = PMC_CPU_INTEL_ICELAKE_XEON; nclasses = 3; break; - case 0x3D: - case 0x47: - cputype = PMC_CPU_INTEL_BROADWELL; - nclasses = 3; - break; - case 0x4f: - case 0x56: - cputype = PMC_CPU_INTEL_BROADWELL_XEON; - nclasses = 3; - break; - case 0x3F: /* Per Intel document 325462-045US 09/2014. */ - case 0x46: /* Per Intel document 325462-045US 09/2014. */ - /* Should 46 be XEON. probably its own? */ - cputype = PMC_CPU_INTEL_HASWELL_XEON; - nclasses = 3; - break; - case 0x3C: /* Per Intel document 325462-045US 01/2013. */ - case 0x45: /* Per Intel document 325462-045US 09/2014. */ - cputype = PMC_CPU_INTEL_HASWELL; + case 0x97: + case 0x9A: + cputype = PMC_CPU_INTEL_ALDERLAKE; nclasses = 3; break; case 0x37: @@ -250,40 +255,9 @@ pmc_intel_initialize(void) error = pmc_tsc_initialize(pmc_mdep, ncpus); if (error) goto error; - switch (cputype) { - /* - * Intel Core, Core 2 and Atom processors. - */ - case PMC_CPU_INTEL_ATOM: - case PMC_CPU_INTEL_ATOM_SILVERMONT: - case PMC_CPU_INTEL_ATOM_GOLDMONT: - case PMC_CPU_INTEL_BROADWELL: - case PMC_CPU_INTEL_BROADWELL_XEON: - case PMC_CPU_INTEL_SKYLAKE_XEON: - case PMC_CPU_INTEL_SKYLAKE: - case PMC_CPU_INTEL_ICELAKE: - case PMC_CPU_INTEL_ICELAKE_XEON: - case PMC_CPU_INTEL_CORE: - case PMC_CPU_INTEL_CORE2: - case PMC_CPU_INTEL_CORE2EXTREME: - case PMC_CPU_INTEL_COREI7: - case PMC_CPU_INTEL_NEHALEM_EX: - case PMC_CPU_INTEL_IVYBRIDGE: - case PMC_CPU_INTEL_SANDYBRIDGE: - case PMC_CPU_INTEL_WESTMERE: - case PMC_CPU_INTEL_WESTMERE_EX: - case PMC_CPU_INTEL_SANDYBRIDGE_XEON: - case PMC_CPU_INTEL_IVYBRIDGE_XEON: - case PMC_CPU_INTEL_HASWELL: - case PMC_CPU_INTEL_HASWELL_XEON: - MPASS(nclasses >= PMC_MDEP_CLASS_INDEX_IAF); - error = pmc_core_initialize(pmc_mdep, ncpus, verov); - break; - - default: - KASSERT(0, ("[intel,%d] Unknown CPU type", __LINE__)); - } + MPASS(nclasses >= PMC_MDEP_CLASS_INDEX_IAF); + error = pmc_core_initialize(pmc_mdep, ncpus, verov); if (error) { pmc_tsc_finalize(pmc_mdep); goto error; @@ -338,34 +312,7 @@ pmc_intel_finalize(struct pmc_mdep *md) { pmc_tsc_finalize(md); - switch (md->pmd_cputype) { - case PMC_CPU_INTEL_ATOM: - case PMC_CPU_INTEL_ATOM_SILVERMONT: - case PMC_CPU_INTEL_ATOM_GOLDMONT: - case PMC_CPU_INTEL_BROADWELL: - case PMC_CPU_INTEL_BROADWELL_XEON: - case PMC_CPU_INTEL_SKYLAKE_XEON: - case PMC_CPU_INTEL_SKYLAKE: - case PMC_CPU_INTEL_ICELAKE: - case PMC_CPU_INTEL_ICELAKE_XEON: - case PMC_CPU_INTEL_CORE: - case PMC_CPU_INTEL_CORE2: - case PMC_CPU_INTEL_CORE2EXTREME: - case PMC_CPU_INTEL_COREI7: - case PMC_CPU_INTEL_NEHALEM_EX: - case PMC_CPU_INTEL_HASWELL: - case PMC_CPU_INTEL_HASWELL_XEON: - case PMC_CPU_INTEL_IVYBRIDGE: - case PMC_CPU_INTEL_SANDYBRIDGE: - case PMC_CPU_INTEL_WESTMERE: - case PMC_CPU_INTEL_WESTMERE_EX: - case PMC_CPU_INTEL_SANDYBRIDGE_XEON: - case PMC_CPU_INTEL_IVYBRIDGE_XEON: - pmc_core_finalize(md); - break; - default: - KASSERT(0, ("[intel,%d] unknown CPU type", __LINE__)); - } + pmc_core_finalize(md); /* * Uncore. diff --git a/sys/sys/pmc.h b/sys/sys/pmc.h index 31b0e6094e04..95107771694a 100644 --- a/sys/sys/pmc.h +++ b/sys/sys/pmc.h @@ -113,6 +113,7 @@ extern char pmc_cpuid[PMC_CPUID_LEN]; __PMC_CPU(INTEL_ATOM_GOLDMONT, 0x9A, "Intel Atom Goldmont") \ __PMC_CPU(INTEL_ICELAKE, 0x9B, "Intel Icelake") \ __PMC_CPU(INTEL_ICELAKE_XEON, 0x9C, "Intel Icelake Xeon") \ + __PMC_CPU(INTEL_ALDERLAKE, 0x9D, "Intel Alderlake") \ __PMC_CPU(INTEL_XSCALE, 0x100, "Intel XScale") \ __PMC_CPU(MIPS_24K, 0x200, "MIPS 24K") \ __PMC_CPU(MIPS_OCTEON, 0x201, "Cavium Octeon") \
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