Date: Mon, 13 Oct 2003 19:47:16 +1000 From: Peter Jeremy <peterjeremy@optushome.com.au> To: Andrew Gallatin <gallatin@cs.duke.edu>, freebsd-hackers@freebsd.org Subject: Re: Determining CPU features / cache organization from userland Message-ID: <20031013094715.GA75662@server.c211-28-27-130.belrs2.nsw.optusnet.com.au> In-Reply-To: <20031012195752.GE2996@saboteur.dek.spc.org> References: <20031010103640.6F5A216A4BF@hub.freebsd.org> <20031010134400.GE803@saboteur.dek.spc.org> <16263.1019.939450.708832@grasshopper.cs.duke.edu> <20031011035827.GD75796@server.c211-28-27-130.belrs2.nsw.optusnet.com.au> <20031011082711.GB679@saboteur.dek.spc.org> <20031011101231.GH75796@server.c211-28-27-130.belrs2.nsw.optusnet.com.au> <20031011140651.GA1739@saboteur.dek.spc.org> <20031012195752.GE2996@saboteur.dek.spc.org>
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On Sun, Oct 12, 2003 at 08:57:52PM +0100, Bruce M Simpson wrote: >[ Andrew: Perhaps you can shed some light on how the necessary information >can be gathered on Alpha? My search was incomplete and I could not find >a reliable source for DEC's development manuals. ] L1 cache information is in the CPU datasheets. I don't know of a summary across the whole Alpha family. The datasheets can be (nominally) found at: http://h18000.www1.hp.com/products/software/alpha-tools/documentation/current/chip-docs.html Last time I went digging, some of the links didn't work but if you look at the links and rummage around the FTP site, the information was all there (and other material that wasn't referenced in the HTML pages). >sysctl is a good interface for retrieving this information as it doesn't >change during the lifetime of the kernel, and it is small. sysctl is already >invoked from within libc to retrieve information in this way. I agree. sysctl would appear to be the best interface. >alpha >----- >Cache discovery? Static. AFAIK, there's no PALcode interface, unfortunately. >i386 pc98 amd64 >--------------- >Cache discovery? CPUID. >Earlier chips which don't support it probably don't have a cache, >or aren't worth supporting. 80386 has no on-chip cache. Intel i486 has 8KB _unified_ 4-way, 16 bytes/line L1. Cache alignment has a significant effect and gcc defaults to 16-byte alignment on -m486. ports/benchmarks/lmbench includes tools that can experimentally determine the cache configuration - though not quickly/efficiently enough to form part of the boot. Peter
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