Date: Wed, 29 Mar 2006 16:02:48 GMT From: Marcel Moolenaar <marcel@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 94248 for review Message-ID: <200603291602.k2TG2mmk048396@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=94248 Change 94248 by marcel@marcel_nfs on 2006/03/29 16:02:20 Change the type of sc_hwmtx to a pointer to struct mtx. Add a new field to the softc (sc_hwmtx_s) that is a struct mtx. We operate on the pointer, which by default will point to the struct. This allows individual bus attachments to preset the mutex pointer to the mutex that we need to use. Have the SCC bus attachment do this. Use uart_[un]lock() instead of mtx_[un]lock_spin() to fully abstract the mutex type (spin or sleep). Affected files ... .. //depot/projects/uart/dev/uart/uart_bus.h#41 edit .. //depot/projects/uart/dev/uart/uart_bus_scc.c#5 edit .. //depot/projects/uart/dev/uart/uart_core.c#48 edit .. //depot/projects/uart/dev/uart/uart_dev_ns8250.c#37 edit .. //depot/projects/uart/dev/uart/uart_dev_sab82532.c#39 edit .. //depot/projects/uart/dev/uart/uart_dev_z8530.c#27 edit Differences ... ==== //depot/projects/uart/dev/uart/uart_bus.h#41 (text+ko) ==== @@ -81,7 +81,8 @@ struct uart_bas sc_bas; device_t sc_dev; - struct mtx sc_hwmtx; /* Spinlock protecting hardware. */ + struct mtx sc_hwmtx_s; /* Spinlock protecting hardware. */ + struct mtx *sc_hwmtx; struct resource *sc_rres; /* Register resource. */ int sc_rrid; ==== //depot/projects/uart/dev/uart/uart_bus_scc.c#5 (text+ko) ==== @@ -43,12 +43,13 @@ #include <dev/uart/uart.h> #include <dev/uart/uart_bus.h> +static int uart_scc_attach(device_t dev); static int uart_scc_probe(device_t dev); static device_method_t uart_scc_methods[] = { /* Device interface */ DEVMETHOD(device_probe, uart_scc_probe), - DEVMETHOD(device_attach, uart_bus_attach), + DEVMETHOD(device_attach, uart_scc_attach), DEVMETHOD(device_detach, uart_bus_detach), /* Serdev interface */ DEVMETHOD(serdev_ihand, uart_bus_ihand), @@ -63,6 +64,22 @@ }; static int +uart_scc_attach(device_t dev) +{ + device_t parent; + struct uart_softc *sc; + uintptr_t mtx; + + parent = device_get_parent(dev); + sc = device_get_softc(dev); + + if (BUS_READ_IVAR(parent, dev, SCC_IVAR_HWMTX, &mtx)) + return (ENXIO); + sc->sc_hwmtx = (struct mtx *)(void *)mtx; + return (uart_bus_attach(dev)); +} + +static int uart_scc_probe(device_t dev) { device_t parent; ==== //depot/projects/uart/dev/uart/uart_core.c#48 (text+ko) ==== @@ -368,7 +368,9 @@ */ sc->sc_leaving = 1; - mtx_init(&sc->sc_hwmtx, "uart_hwmtx", NULL, MTX_SPIN); + mtx_init(&sc->sc_hwmtx_s, "uart_hwmtx", NULL, MTX_SPIN); + if (sc->sc_hwmtx == NULL) + sc->sc_hwmtx = &sc->sc_hwmtx_s; /* * Re-allocate. We expect that the softc contains the information @@ -377,7 +379,7 @@ sc->sc_rres = bus_alloc_resource(dev, sc->sc_rtype, &sc->sc_rrid, 0, ~0, sc->sc_class->uc_range, RF_ACTIVE); if (sc->sc_rres == NULL) { - mtx_destroy(&sc->sc_hwmtx); + mtx_destroy(&sc->sc_hwmtx_s); return (ENXIO); } sc->sc_bas.bsh = rman_get_bushandle(sc->sc_rres); @@ -481,7 +483,7 @@ goto fail; if (sc->sc_sysdev != NULL) - sc->sc_sysdev->hwmtx = &sc->sc_hwmtx; + sc->sc_sysdev->hwmtx = sc->sc_hwmtx; sc->sc_leaving = 0; uart_intr(sc); @@ -498,7 +500,7 @@ } bus_release_resource(dev, sc->sc_rtype, sc->sc_rrid, sc->sc_rres); - mtx_destroy(&sc->sc_hwmtx); + mtx_destroy(&sc->sc_hwmtx_s); return (error); } @@ -532,7 +534,7 @@ } bus_release_resource(dev, sc->sc_rtype, sc->sc_rrid, sc->sc_rres); - mtx_destroy(&sc->sc_hwmtx); + mtx_destroy(&sc->sc_hwmtx_s); if (sc->sc_class->size > sizeof(*sc)) { device_set_softc(dev, NULL); ==== //depot/projects/uart/dev/uart/uart_dev_ns8250.c#37 (text+ko) ==== @@ -432,7 +432,7 @@ int error; bas = &sc->sc_bas; - mtx_lock_spin(&sc->sc_hwmtx); + uart_lock(sc->sc_hwmtx); if (sc->sc_hasfifo) { ns8250_flush(bas, what); uart_setreg(bas, REG_FCR, ns8250->fcr); @@ -440,7 +440,7 @@ error = 0; } else error = ns8250_drain(bas, what); - mtx_unlock_spin(&sc->sc_hwmtx); + uart_unlock(sc->sc_hwmtx); return (error); } @@ -453,9 +453,9 @@ do { old = sc->sc_hwsig; sig = old; - mtx_lock_spin(&sc->sc_hwmtx); + uart_lock(sc->sc_hwmtx); msr = uart_getreg(&sc->sc_bas, REG_MSR); - mtx_unlock_spin(&sc->sc_hwmtx); + uart_unlock(sc->sc_hwmtx); SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR); SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS); SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD); @@ -474,7 +474,7 @@ bas = &sc->sc_bas; error = 0; - mtx_lock_spin(&sc->sc_hwmtx); + uart_lock(sc->sc_hwmtx); switch (request) { case UART_IOCTL_BREAK: lcr = uart_getreg(bas, REG_LCR); @@ -533,7 +533,7 @@ error = EINVAL; break; } - mtx_unlock_spin(&sc->sc_hwmtx); + uart_unlock(sc->sc_hwmtx); return (error); } @@ -545,16 +545,16 @@ uint8_t iir, lsr; bas = &sc->sc_bas; - mtx_lock_spin(&sc->sc_hwmtx); + uart_lock(sc->sc_hwmtx); iir = uart_getreg(bas, REG_IIR); if (iir & IIR_NOPEND) { - mtx_unlock_spin(&sc->sc_hwmtx); + uart_unlock(sc->sc_hwmtx); return (0); } ipend = 0; if (iir & IIR_RXRDY) { lsr = uart_getreg(bas, REG_LSR); - mtx_unlock_spin(&sc->sc_hwmtx); + uart_unlock(sc->sc_hwmtx); if (lsr & LSR_OE) ipend |= SER_INT_OVERRUN; if (lsr & LSR_BI) @@ -562,7 +562,7 @@ if (lsr & LSR_RXRDY) ipend |= SER_INT_RXREADY; } else { - mtx_unlock_spin(&sc->sc_hwmtx); + uart_unlock(sc->sc_hwmtx); if (iir & IIR_TXRDY) ipend |= SER_INT_TXIDLE; else @@ -579,9 +579,9 @@ int error; bas = &sc->sc_bas; - mtx_lock_spin(&sc->sc_hwmtx); + uart_lock(sc->sc_hwmtx); error = ns8250_param(bas, baudrate, databits, stopbits, parity); - mtx_unlock_spin(&sc->sc_hwmtx); + uart_unlock(sc->sc_hwmtx); return (error); } @@ -740,7 +740,7 @@ uint8_t lsr; bas = &sc->sc_bas; - mtx_lock_spin(&sc->sc_hwmtx); + uart_lock(sc->sc_hwmtx); lsr = uart_getreg(bas, REG_LSR); while (lsr & LSR_RXRDY) { if (uart_rx_full(sc)) { @@ -761,7 +761,7 @@ uart_barrier(bas); lsr = uart_getreg(bas, REG_LSR); } - mtx_unlock_spin(&sc->sc_hwmtx); + uart_unlock(sc->sc_hwmtx); return (0); } @@ -785,7 +785,7 @@ SER_DRTS); } } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); - mtx_lock_spin(&sc->sc_hwmtx); + uart_lock(sc->sc_hwmtx); ns8250->mcr &= ~(MCR_DTR|MCR_RTS); if (new & SER_DTR) ns8250->mcr |= MCR_DTR; @@ -793,7 +793,7 @@ ns8250->mcr |= MCR_RTS; uart_setreg(bas, REG_MCR, ns8250->mcr); uart_barrier(bas); - mtx_unlock_spin(&sc->sc_hwmtx); + uart_unlock(sc->sc_hwmtx); return (0); } @@ -805,7 +805,7 @@ int i; bas = &sc->sc_bas; - mtx_lock_spin(&sc->sc_hwmtx); + uart_lock(sc->sc_hwmtx); while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) ; uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY); @@ -815,6 +815,6 @@ uart_barrier(bas); } sc->sc_txbusy = 1; - mtx_unlock_spin(&sc->sc_hwmtx); + uart_unlock(sc->sc_hwmtx); return (0); } ==== //depot/projects/uart/dev/uart/uart_dev_sab82532.c#39 (text+ko) ==== @@ -437,9 +437,9 @@ sab82532_bus_flush(struct uart_softc *sc, int what) { - mtx_lock_spin(&sc->sc_hwmtx); + uart_lock(sc->sc_hwmtx); sab82532_flush(&sc->sc_bas, what); - mtx_unlock_spin(&sc->sc_hwmtx); + uart_unlock(sc->sc_hwmtx); return (0); } @@ -454,7 +454,7 @@ do { old = sc->sc_hwsig; sig = old; - mtx_lock_spin(&sc->sc_hwmtx); + uart_lock(sc->sc_hwmtx); star = uart_getreg(bas, SAB_STAR); SIGCHG(star & SAB_STAR_CTS, sig, SER_CTS, SER_DCTS); vstr = uart_getreg(bas, SAB_VSTR); @@ -469,7 +469,7 @@ break; } SIGCHG(pvr, sig, SER_DSR, SER_DDSR); - mtx_unlock_spin(&sc->sc_hwmtx); + uart_unlock(sc->sc_hwmtx); new = sig & ~SER_MASK_DELTA; } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); return (sig); @@ -484,7 +484,7 @@ bas = &sc->sc_bas; error = 0; - mtx_lock_spin(&sc->sc_hwmtx); + uart_lock(sc->sc_hwmtx); switch (request) { case UART_IOCTL_BREAK: dafo = uart_getreg(bas, SAB_DAFO); @@ -520,7 +520,7 @@ error = EINVAL; break; } - mtx_unlock_spin(&sc->sc_hwmtx); + uart_unlock(sc->sc_hwmtx); return (error); } @@ -532,7 +532,7 @@ uint8_t isr0, isr1; bas = &sc->sc_bas; - mtx_lock_spin(&sc->sc_hwmtx); + uart_lock(sc->sc_hwmtx); isr0 = uart_getreg(bas, SAB_ISR0); isr1 = uart_getreg(bas, SAB_ISR1); uart_barrier(bas); @@ -542,7 +542,7 @@ uart_setreg(bas, SAB_CMDR, SAB_CMDR_RFRD); uart_barrier(bas); } - mtx_unlock_spin(&sc->sc_hwmtx); + uart_unlock(sc->sc_hwmtx); ipend = 0; if (isr1 & SAB_ISR1_BRKT) @@ -567,9 +567,9 @@ int error; bas = &sc->sc_bas; - mtx_lock_spin(&sc->sc_hwmtx); + uart_lock(sc->sc_hwmtx); error = sab82532_param(bas, baudrate, databits, stopbits, parity); - mtx_unlock_spin(&sc->sc_hwmtx); + uart_unlock(sc->sc_hwmtx); return (error); } @@ -617,7 +617,7 @@ uint8_t s; bas = &sc->sc_bas; - mtx_lock_spin(&sc->sc_hwmtx); + uart_lock(sc->sc_hwmtx); if (uart_getreg(bas, SAB_STAR) & SAB_STAR_RFNE) { rbcl = uart_getreg(bas, SAB_RBCL) & 31; if (rbcl == 0) @@ -641,7 +641,7 @@ ; uart_setreg(bas, SAB_CMDR, SAB_CMDR_RMC); uart_barrier(bas); - mtx_unlock_spin(&sc->sc_hwmtx); + uart_unlock(sc->sc_hwmtx); return (0); } @@ -666,7 +666,7 @@ } } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); - mtx_lock_spin(&sc->sc_hwmtx); + uart_lock(sc->sc_hwmtx); /* Set DTR pin. */ pvr = uart_getreg(bas, SAB_PVR); switch (bas->chan) { @@ -693,7 +693,7 @@ mode |= SAB_MODE_FRTS; uart_setreg(bas, SAB_MODE, mode); uart_barrier(bas); - mtx_unlock_spin(&sc->sc_hwmtx); + uart_unlock(sc->sc_hwmtx); return (0); } @@ -704,7 +704,7 @@ int i; bas = &sc->sc_bas; - mtx_lock_spin(&sc->sc_hwmtx); + uart_lock(sc->sc_hwmtx); while (!(uart_getreg(bas, SAB_STAR) & SAB_STAR_XFW)) ; for (i = 0; i < sc->sc_txdatasz; i++) @@ -714,6 +714,6 @@ ; uart_setreg(bas, SAB_CMDR, SAB_CMDR_XF); sc->sc_txbusy = 1; - mtx_unlock_spin(&sc->sc_hwmtx); + uart_unlock(sc->sc_hwmtx); return (0); } ==== //depot/projects/uart/dev/uart/uart_dev_z8530.c#27 (text+ko) ==== @@ -348,9 +348,9 @@ do { old = sc->sc_hwsig; sig = old; - mtx_lock_spin(&sc->sc_hwmtx); + uart_lock(sc->sc_hwmtx); bes = uart_getmreg(&sc->sc_bas, RR_BES); - mtx_unlock_spin(&sc->sc_hwmtx); + uart_unlock(sc->sc_hwmtx); SIGCHG(bes & BES_CTS, sig, SER_CTS, SER_DCTS); SIGCHG(bes & BES_DCD, sig, SER_DCD, SER_DDCD); SIGCHG(bes & BES_SYNC, sig, SER_DSR, SER_DDSR); @@ -368,7 +368,7 @@ bas = &sc->sc_bas; error = 0; - mtx_lock_spin(&sc->sc_hwmtx); + uart_lock(sc->sc_hwmtx); switch (request) { case UART_IOCTL_BREAK: if (data) @@ -382,7 +382,7 @@ error = EINVAL; break; } - mtx_unlock_spin(&sc->sc_hwmtx); + uart_unlock(sc->sc_hwmtx); return (error); } @@ -398,7 +398,7 @@ bas = &sc->sc_bas; ipend = 0; - mtx_lock_spin(&sc->sc_hwmtx); + uart_lock(sc->sc_hwmtx); switch (bas->chan) { case 1: ip = uart_getmreg(bas, RR_IP); @@ -454,7 +454,7 @@ uart_barrier(bas); } - mtx_unlock_spin(&sc->sc_hwmtx); + uart_unlock(sc->sc_hwmtx); return (ipend); } @@ -466,10 +466,10 @@ struct z8530_softc *z8530 = (struct z8530_softc*)sc; int error; - mtx_lock_spin(&sc->sc_hwmtx); + uart_lock(sc->sc_hwmtx); error = z8530_param(&sc->sc_bas, baudrate, databits, stopbits, parity, &z8530->tpc); - mtx_unlock_spin(&sc->sc_hwmtx); + uart_unlock(sc->sc_hwmtx); return (error); } @@ -499,7 +499,7 @@ uint8_t bes, src; bas = &sc->sc_bas; - mtx_lock_spin(&sc->sc_hwmtx); + uart_lock(sc->sc_hwmtx); bes = uart_getmreg(bas, RR_BES); while (bes & BES_RXA) { if (uart_rx_full(sc)) { @@ -533,7 +533,7 @@ } bes = uart_getmreg(bas, RR_BES); } - mtx_unlock_spin(&sc->sc_hwmtx); + uart_unlock(sc->sc_hwmtx); return (0); } @@ -558,7 +558,7 @@ } } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); - mtx_lock_spin(&sc->sc_hwmtx); + uart_lock(sc->sc_hwmtx); if (new & SER_DTR) z8530->tpc |= TPC_DTR; else @@ -569,7 +569,7 @@ z8530->tpc &= ~TPC_RTS; uart_setmreg(bas, WR_TPC, z8530->tpc); uart_barrier(bas); - mtx_unlock_spin(&sc->sc_hwmtx); + uart_unlock(sc->sc_hwmtx); return (0); } @@ -580,13 +580,13 @@ struct uart_bas *bas; bas = &sc->sc_bas; - mtx_lock_spin(&sc->sc_hwmtx); + uart_lock(sc->sc_hwmtx); while (!(uart_getmreg(bas, RR_BES) & BES_TXE)) ; uart_setreg(bas, REG_DATA, sc->sc_txbuf[0]); uart_barrier(bas); sc->sc_txbusy = 1; z8530->txidle = 1; /* Report SER_INT_TXIDLE again. */ - mtx_unlock_spin(&sc->sc_hwmtx); + uart_unlock(sc->sc_hwmtx); return (0); }
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