Date: Sun, 3 Nov 2019 21:14:09 +0000 (UTC) From: Vladimir Kondratyev <wulf@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r354318 - head/sys/dev/ichiic Message-ID: <201911032114.xA3LE9xI077819@repo.freebsd.org>
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Author: wulf Date: Sun Nov 3 21:14:08 2019 New Revision: 354318 URL: https://svnweb.freebsd.org/changeset/base/354318 Log: [ig4] Minor improvement of write pipelining With leaving some data queued in the TX FIFO at the end of write cycle. Modified: head/sys/dev/ichiic/ig4_iic.c Modified: head/sys/dev/ichiic/ig4_iic.c ============================================================================== --- head/sys/dev/ichiic/ig4_iic.c Sun Nov 3 21:12:59 2019 (r354317) +++ head/sys/dev/ichiic/ig4_iic.c Sun Nov 3 21:14:08 2019 (r354318) @@ -471,6 +471,7 @@ ig4iic_write(ig4iic_softc_t *sc, uint8_t *buf, uint16_ int sent = 0; int burst, target; int error; + bool lowat_set = false; if (len == 0) return (0); @@ -479,6 +480,11 @@ ig4iic_write(ig4iic_softc_t *sc, uint8_t *buf, uint16_ burst = sc->cfg.txfifo_depth - (reg_read(sc, IG4_REG_TXFLR) & IG4_FIFOLVL_MASK); target = MIN(sent + burst, (int)len); + /* Leave some data queued to maintain the hardware pipeline */ + if (!lowat_set && target != len) { + lowat_set = true; + reg_write(sc, IG4_REG_TX_TL, IG4_FIFO_LOWAT); + } while(sent < target) { cmd = buf[sent]; if (repeated_start && sent == 0) @@ -494,6 +500,8 @@ ig4iic_write(ig4iic_softc_t *sc, uint8_t *buf, uint16_ break; } } + if (lowat_set) + reg_write(sc, IG4_REG_TX_TL, 0); return (error); }
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