Date: Mon, 4 Oct 2021 19:19:32 GMT From: Yuri Victorovich <yuri@FreeBSD.org> To: ports-committers@FreeBSD.org, dev-commits-ports-all@FreeBSD.org, dev-commits-ports-main@FreeBSD.org Subject: git: d5ec1b970b86 - main - cad/yosys: Update 0.9 -> 0.10 Message-ID: <202110041919.194JJWDS050574@gitrepo.freebsd.org>
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The branch main has been updated by yuri: URL: https://cgit.FreeBSD.org/ports/commit/?id=d5ec1b970b865309f72749333b8a22261e710dcf commit d5ec1b970b865309f72749333b8a22261e710dcf Author: Yuri Victorovich <yuri@FreeBSD.org> AuthorDate: 2021-10-04 16:28:51 +0000 Commit: Yuri Victorovich <yuri@FreeBSD.org> CommitDate: 2021-10-04 19:18:26 +0000 cad/yosys: Update 0.9 -> 0.10 --- cad/yosys/Makefile | 3 +- cad/yosys/distinfo | 6 +-- cad/yosys/pkg-plist | 144 +++++++++++++++++++++++++++++++++++++++++++--------- 3 files changed, 125 insertions(+), 28 deletions(-) diff --git a/cad/yosys/Makefile b/cad/yosys/Makefile index dba03b40cb7e..2c00de143e99 100644 --- a/cad/yosys/Makefile +++ b/cad/yosys/Makefile @@ -2,8 +2,7 @@ PORTNAME= yosys DISTVERSIONPREFIX= yosys- -DISTVERSION= 0.9 -PORTREVISION= 1 +DISTVERSION= 0.10 CATEGORIES= cad MAINTAINER= yuri@FreeBSD.org diff --git a/cad/yosys/distinfo b/cad/yosys/distinfo index 11ac85bfe1a8..22c04a7b0e66 100644 --- a/cad/yosys/distinfo +++ b/cad/yosys/distinfo @@ -1,3 +1,3 @@ -TIMESTAMP = 1571641858 -SHA256 (YosysHQ-yosys-yosys-0.9_GH0.tar.gz) = f2e31371f9cf1b36cb4f57b23fd6eb849adc7d935dcf49f3c905aa5136382c2f -SIZE (YosysHQ-yosys-yosys-0.9_GH0.tar.gz) = 1299545 +TIMESTAMP = 1633363221 +SHA256 (YosysHQ-yosys-yosys-0.10_GH0.tar.gz) = eeec77e1983fd978fbff0257c4f4fb0d9bc07e403a13b9fc467878df3467b191 +SIZE (YosysHQ-yosys-yosys-0.10_GH0.tar.gz) = 2020669 diff --git a/cad/yosys/pkg-plist b/cad/yosys/pkg-plist index 14438be30a62..26ba829f1ea5 100644 --- a/cad/yosys/pkg-plist +++ b/cad/yosys/pkg-plist @@ -2,48 +2,64 @@ bin/yosys bin/yosys-config bin/yosys-filterlib bin/yosys-smtbmc +%%DATADIR%%/abc9_map.v +%%DATADIR%%/abc9_model.v +%%DATADIR%%/abc9_unmap.v %%DATADIR%%/achronix/speedster22i/cells_map.v %%DATADIR%%/achronix/speedster22i/cells_sim.v %%DATADIR%%/adff2dff.v %%DATADIR%%/anlogic/arith_map.v %%DATADIR%%/anlogic/cells_map.v %%DATADIR%%/anlogic/cells_sim.v -%%DATADIR%%/anlogic/dram_init_16x4.vh -%%DATADIR%%/anlogic/drams.txt -%%DATADIR%%/anlogic/drams_map.v %%DATADIR%%/anlogic/eagle_bb.v +%%DATADIR%%/anlogic/lutram_init_16x4.vh +%%DATADIR%%/anlogic/lutrams.txt +%%DATADIR%%/anlogic/lutrams_map.v %%DATADIR%%/cells.lib +%%DATADIR%%/cmp2lcu.v %%DATADIR%%/cmp2lut.v +%%DATADIR%%/coolrunner2/cells_counter_map.v %%DATADIR%%/coolrunner2/cells_latch.v %%DATADIR%%/coolrunner2/cells_sim.v %%DATADIR%%/coolrunner2/tff_extract.v %%DATADIR%%/coolrunner2/xc2_dff.lib %%DATADIR%%/dff2ff.v %%DATADIR%%/ecp5/arith_map.v -%%DATADIR%%/ecp5/bram.txt %%DATADIR%%/ecp5/bram_conn_1.vh %%DATADIR%%/ecp5/bram_conn_18.vh %%DATADIR%%/ecp5/bram_conn_2.vh +%%DATADIR%%/ecp5/bram_conn_36.vh %%DATADIR%%/ecp5/bram_conn_4.vh %%DATADIR%%/ecp5/bram_conn_9.vh %%DATADIR%%/ecp5/bram_init_1_2_4.vh %%DATADIR%%/ecp5/bram_init_9_18_36.vh +%%DATADIR%%/ecp5/brams.txt %%DATADIR%%/ecp5/brams_map.v %%DATADIR%%/ecp5/cells_bb.v +%%DATADIR%%/ecp5/cells_ff.vh +%%DATADIR%%/ecp5/cells_io.vh %%DATADIR%%/ecp5/cells_map.v %%DATADIR%%/ecp5/cells_sim.v -%%DATADIR%%/ecp5/dram.txt -%%DATADIR%%/ecp5/drams_map.v +%%DATADIR%%/ecp5/dsp_map.v %%DATADIR%%/ecp5/latches_map.v +%%DATADIR%%/ecp5/lutrams.txt +%%DATADIR%%/ecp5/lutrams_map.v +%%DATADIR%%/efinix/arith_map.v +%%DATADIR%%/efinix/brams.txt +%%DATADIR%%/efinix/brams_map.v +%%DATADIR%%/efinix/cells_map.v +%%DATADIR%%/efinix/cells_sim.v +%%DATADIR%%/efinix/gbuf_map.v %%DATADIR%%/gate2lut.v %%DATADIR%%/gowin/arith_map.v -%%DATADIR%%/gowin/bram.txt +%%DATADIR%%/gowin/bram_init_16.vh +%%DATADIR%%/gowin/brams.txt %%DATADIR%%/gowin/brams_init3.vh %%DATADIR%%/gowin/brams_map.v %%DATADIR%%/gowin/cells_map.v %%DATADIR%%/gowin/cells_sim.v -%%DATADIR%%/gowin/dram.txt -%%DATADIR%%/gowin/drams_map.v +%%DATADIR%%/gowin/lutrams.txt +%%DATADIR%%/gowin/lutrams_map.v %%DATADIR%%/greenpak4/cells_blackbox.v %%DATADIR%%/greenpak4/cells_latch.v %%DATADIR%%/greenpak4/cells_map.v @@ -52,6 +68,7 @@ bin/yosys-smtbmc %%DATADIR%%/greenpak4/cells_sim_digital.v %%DATADIR%%/greenpak4/cells_sim_wip.v %%DATADIR%%/greenpak4/gp_dff.lib +%%DATADIR%%/ice40/abc9_model.v %%DATADIR%%/ice40/arith_map.v %%DATADIR%%/ice40/brams.txt %%DATADIR%%/ice40/brams_init1.vh @@ -60,16 +77,32 @@ bin/yosys-smtbmc %%DATADIR%%/ice40/brams_map.v %%DATADIR%%/ice40/cells_map.v %%DATADIR%%/ice40/cells_sim.v +%%DATADIR%%/ice40/dsp_map.v +%%DATADIR%%/ice40/ff_map.v %%DATADIR%%/ice40/latches_map.v -%%DATADIR%%/include/backends/ilang/ilang_backend.h +%%DATADIR%%/include/backends/cxxrtl/cxxrtl.h +%%DATADIR%%/include/backends/cxxrtl/cxxrtl_capi.cc +%%DATADIR%%/include/backends/cxxrtl/cxxrtl_capi.h +%%DATADIR%%/include/backends/cxxrtl/cxxrtl_vcd.h +%%DATADIR%%/include/backends/cxxrtl/cxxrtl_vcd_capi.cc +%%DATADIR%%/include/backends/cxxrtl/cxxrtl_vcd_capi.h +%%DATADIR%%/include/backends/rtlil/rtlil_backend.h %%DATADIR%%/include/frontends/ast/ast.h +%%DATADIR%%/include/frontends/ast/ast_binding.h +%%DATADIR%%/include/frontends/blif/blifparse.h +%%DATADIR%%/include/kernel/binding.h %%DATADIR%%/include/kernel/celledges.h %%DATADIR%%/include/kernel/celltypes.h %%DATADIR%%/include/kernel/consteval.h +%%DATADIR%%/include/kernel/constids.inc +%%DATADIR%%/include/kernel/ff.h +%%DATADIR%%/include/kernel/ffinit.h %%DATADIR%%/include/kernel/hashlib.h %%DATADIR%%/include/kernel/log.h %%DATADIR%%/include/kernel/macc.h +%%DATADIR%%/include/kernel/mem.h %%DATADIR%%/include/kernel/modtools.h +%%DATADIR%%/include/kernel/qcsat.h %%DATADIR%%/include/kernel/register.h %%DATADIR%%/include/kernel/rtlil.h %%DATADIR%%/include/kernel/satgen.h @@ -78,44 +111,109 @@ bin/yosys-smtbmc %%DATADIR%%/include/kernel/yosys.h %%DATADIR%%/include/libs/ezsat/ezminisat.h %%DATADIR%%/include/libs/ezsat/ezsat.h +%%DATADIR%%/include/libs/json11/json11.hpp %%DATADIR%%/include/libs/sha1/sha1.h %%DATADIR%%/include/passes/fsm/fsmdata.h -%%DATADIR%%/intel/a10gx/cells_map.v -%%DATADIR%%/intel/a10gx/cells_sim.v %%DATADIR%%/intel/common/altpll_bb.v -%%DATADIR%%/intel/common/brams.txt -%%DATADIR%%/intel/common/brams_map.v +%%DATADIR%%/intel/common/brams_m9k.txt +%%DATADIR%%/intel/common/brams_map_m9k.v +%%DATADIR%%/intel/common/ff_map.v %%DATADIR%%/intel/common/m9k_bb.v -%%DATADIR%%/intel/cyclone10/cells_map.v -%%DATADIR%%/intel/cyclone10/cells_sim.v +%%DATADIR%%/intel/cyclone10lp/cells_map.v +%%DATADIR%%/intel/cyclone10lp/cells_sim.v %%DATADIR%%/intel/cycloneiv/cells_map.v %%DATADIR%%/intel/cycloneiv/cells_sim.v %%DATADIR%%/intel/cycloneive/cells_map.v %%DATADIR%%/intel/cycloneive/cells_sim.v -%%DATADIR%%/intel/cyclonev/cells_map.v -%%DATADIR%%/intel/cyclonev/cells_sim.v %%DATADIR%%/intel/max10/cells_map.v %%DATADIR%%/intel/max10/cells_sim.v +%%DATADIR%%/intel_alm/common/abc9_map.v +%%DATADIR%%/intel_alm/common/abc9_model.v +%%DATADIR%%/intel_alm/common/abc9_unmap.v +%%DATADIR%%/intel_alm/common/alm_map.v +%%DATADIR%%/intel_alm/common/alm_sim.v +%%DATADIR%%/intel_alm/common/arith_alm_map.v +%%DATADIR%%/intel_alm/common/bram_m10k.txt +%%DATADIR%%/intel_alm/common/bram_m20k.txt +%%DATADIR%%/intel_alm/common/bram_m20k_map.v +%%DATADIR%%/intel_alm/common/dff_map.v +%%DATADIR%%/intel_alm/common/dff_sim.v +%%DATADIR%%/intel_alm/common/dsp_map.v +%%DATADIR%%/intel_alm/common/dsp_sim.v +%%DATADIR%%/intel_alm/common/lutram_mlab.txt +%%DATADIR%%/intel_alm/common/megafunction_bb.v +%%DATADIR%%/intel_alm/common/mem_sim.v +%%DATADIR%%/intel_alm/common/misc_sim.v +%%DATADIR%%/intel_alm/common/quartus_rename.v +%%DATADIR%%/intel_alm/cyclonev/cells_sim.v +%%DATADIR%%/machxo2/cells_map.v +%%DATADIR%%/machxo2/cells_sim.v +%%DATADIR%%/mul2dsp.v +%%DATADIR%%/nexus/arith_map.v +%%DATADIR%%/nexus/brams.txt +%%DATADIR%%/nexus/brams_init.vh +%%DATADIR%%/nexus/brams_map.v +%%DATADIR%%/nexus/cells_map.v +%%DATADIR%%/nexus/cells_sim.v +%%DATADIR%%/nexus/cells_xtra.v +%%DATADIR%%/nexus/dsp_map.v +%%DATADIR%%/nexus/latches_map.v +%%DATADIR%%/nexus/lrams.txt +%%DATADIR%%/nexus/lrams_init.vh +%%DATADIR%%/nexus/lrams_map.v +%%DATADIR%%/nexus/lutrams.txt +%%DATADIR%%/nexus/lutrams_map.v +%%DATADIR%%/nexus/parse_init.vh %%DATADIR%%/pmux2mux.v %%DATADIR%%/python3/smtio.py +%%DATADIR%%/quicklogic/abc9_map.v +%%DATADIR%%/quicklogic/abc9_model.v +%%DATADIR%%/quicklogic/abc9_unmap.v +%%DATADIR%%/quicklogic/cells_sim.v +%%DATADIR%%/quicklogic/lut_sim.v +%%DATADIR%%/quicklogic/pp3_cells_map.v +%%DATADIR%%/quicklogic/pp3_cells_sim.v +%%DATADIR%%/quicklogic/pp3_ffs_map.v +%%DATADIR%%/quicklogic/pp3_latches_map.v +%%DATADIR%%/quicklogic/pp3_lut_map.v %%DATADIR%%/sf2/arith_map.v %%DATADIR%%/sf2/cells_map.v %%DATADIR%%/sf2/cells_sim.v %%DATADIR%%/simcells.v %%DATADIR%%/simlib.v %%DATADIR%%/techmap.v +%%DATADIR%%/xilinx/abc9_model.v %%DATADIR%%/xilinx/arith_map.v -%%DATADIR%%/xilinx/brams.txt -%%DATADIR%%/xilinx/brams_bb.v %%DATADIR%%/xilinx/brams_init_16.vh %%DATADIR%%/xilinx/brams_init_18.vh %%DATADIR%%/xilinx/brams_init_32.vh %%DATADIR%%/xilinx/brams_init_36.vh -%%DATADIR%%/xilinx/brams_map.v +%%DATADIR%%/xilinx/brams_init_8.vh +%%DATADIR%%/xilinx/brams_init_9.vh %%DATADIR%%/xilinx/cells_map.v %%DATADIR%%/xilinx/cells_sim.v %%DATADIR%%/xilinx/cells_xtra.v -%%DATADIR%%/xilinx/drams.txt -%%DATADIR%%/xilinx/drams_map.v %%DATADIR%%/xilinx/ff_map.v +%%DATADIR%%/xilinx/lut4_lutrams.txt +%%DATADIR%%/xilinx/lut6_lutrams.txt %%DATADIR%%/xilinx/lut_map.v +%%DATADIR%%/xilinx/lutrams_map.v +%%DATADIR%%/xilinx/mux_map.v +%%DATADIR%%/xilinx/xc2v_brams.txt +%%DATADIR%%/xilinx/xc2v_brams_map.v +%%DATADIR%%/xilinx/xc3s_mult_map.v +%%DATADIR%%/xilinx/xc3sa_brams.txt +%%DATADIR%%/xilinx/xc3sda_brams.txt +%%DATADIR%%/xilinx/xc3sda_dsp_map.v +%%DATADIR%%/xilinx/xc4v_dsp_map.v +%%DATADIR%%/xilinx/xc5v_dsp_map.v +%%DATADIR%%/xilinx/xc6s_brams.txt +%%DATADIR%%/xilinx/xc6s_brams_map.v +%%DATADIR%%/xilinx/xc6s_dsp_map.v +%%DATADIR%%/xilinx/xc7_brams_map.v +%%DATADIR%%/xilinx/xc7_dsp_map.v +%%DATADIR%%/xilinx/xc7_xcu_brams.txt +%%DATADIR%%/xilinx/xcu_brams_map.v +%%DATADIR%%/xilinx/xcu_dsp_map.v +%%DATADIR%%/xilinx/xcup_urams.txt +%%DATADIR%%/xilinx/xcup_urams_map.v
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