Date: Tue, 9 Feb 2021 12:12:20 GMT From: Michal Meloun <mmel@FreeBSD.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org Subject: git: ec090f4a6765 - main - arm32: Align arguments of sync_icache() syscall to cacheline size. Message-ID: <202102091212.119CCKkv096687@gitrepo.freebsd.org>
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The branch main has been updated by mmel: URL: https://cgit.FreeBSD.org/src/commit/?id=ec090f4a67654fa541e6d97fd5f74d3f66c1c0d0 commit ec090f4a67654fa541e6d97fd5f74d3f66c1c0d0 Author: Michal Meloun <mmel@FreeBSD.org> AuthorDate: 2021-02-09 10:36:36 +0000 Commit: Michal Meloun <mmel@FreeBSD.org> CommitDate: 2021-02-09 11:53:09 +0000 arm32: Align arguments of sync_icache() syscall to cacheline size. Otherwise, we may miss synchronization of the last cacheline. MFC after: 3 days --- sys/arm/arm/sys_machdep.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/sys/arm/arm/sys_machdep.c b/sys/arm/arm/sys_machdep.c index d33ac75ad73b..fc424d0fad39 100644 --- a/sys/arm/arm/sys_machdep.c +++ b/sys/arm/arm/sys_machdep.c @@ -68,12 +68,9 @@ sync_icache(uintptr_t addr, size_t len) size_t size; vm_offset_t rv; - /* - * Align starting address to even number because value of "1" - * is used as return value for success. - */ - len += addr & 1; - addr &= ~1; + /* Align starting address to cacheline size */ + len += addr & cpuinfo.dcache_line_mask; + addr &= ~cpuinfo.dcache_line_mask; /* Break whole range to pages. */ do {
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