Date: Sat, 10 May 2014 12:52:23 -0600 From: Ian Lepore <ian@FreeBSD.org> To: Mark R V Murray <markm@FreeBSD.org> Cc: freebsd-arm <freebsd-arm@FreeBSD.org> Subject: Re: Fast cycle counter for ARM chips with SCC - patch for review. Message-ID: <1399747943.22079.415.camel@revolution.hippie.lan> In-Reply-To: <22E12094-E6B2-42F9-94AB-014A702D17F2@FreeBSD.org> References: <22E12094-E6B2-42F9-94AB-014A702D17F2@FreeBSD.org>
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On Sat, 2014-05-10 at 18:39 +0100, Mark R V Murray wrote: > Hi * >=20 > This patch makes the ARM6 kernels that have an SCC coprocessor (RPI and= WANDBOARD have them) get a MUCH better implementation of get_cyclecount(= 9), but not a perfect one. The incrementing rate is good (+- 1 per instru= ction), but its only 32 bits. Later, if there is interest, I may wish to = fix that with an overflow interrupt, but for now its easily good enough f= or the kernel entropy harvesting service. Also, its MUUUCH more efficient= ; a simple read rather can calling the internal kernel binuptime(9) clock. >=20 > Comments, please? I=A2m keen to commit. >=20 > M The manual says setting the user enable bit doesn't just enable user read, it also grants user write access to most of the registers, including CCNT. The value to write to PMINTENCLR should be 0xffffffff. In theory you should read the ID register to see how many counters are available and set that many of the low-order bits to 1, but the manual says that writes are ignored for the bits 30-N so you can just blindly write all ones. For PMCNTENSET I think the value to write is 0x80000000, no need to enable other counters. The comment says PMCR is set to 1, but it's actually set to 7. The comment=20 This '#if' asks the question 'Do we have a System Control Coprocessor? should read something like 'Does CP15 include performance counters?' all arm chips have a system control coprocessor. -- Ian
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