Date: Mon, 12 Jul 2021 04:29:19 GMT From: Gordon Bergling <gbe@FreeBSD.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org Subject: git: 0b1293252543 - main - pmc(3): mandoc clean ups Message-ID: <202107120429.16C4TJX5098952@gitrepo.freebsd.org>
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The branch main has been updated by gbe (doc committer): URL: https://cgit.FreeBSD.org/src/commit/?id=0b1293252543802b809b5f13f554e5d6391d3445 commit 0b1293252543802b809b5f13f554e5d6391d3445 Author: Gordon Bergling <gbe@FreeBSD.org> AuthorDate: 2021-07-12 04:28:03 +0000 Commit: Gordon Bergling <gbe@FreeBSD.org> CommitDate: 2021-07-12 04:28:03 +0000 pmc(3): mandoc clean ups - new sentence, new line - tab in filled text - unusual Xr order - skipping paragraph macro: Pp before Ss Reviewed by: bcr MFC after: 1 week Differential Revision: https://reviews.freebsd.org/D31143 --- lib/libpmc/pmc.corei7.3 | 488 +++++++++++++++++++++------------------ lib/libpmc/pmc.corei7uc.3 | 377 ++++++++++++++++-------------- lib/libpmc/pmc.haswell.3 | 132 +++++------ lib/libpmc/pmc.haswelluc.3 | 17 +- lib/libpmc/pmc.haswellxeon.3 | 138 +++++------ lib/libpmc/pmc.iaf.3 | 1 - lib/libpmc/pmc.ivybridge.3 | 88 +++---- lib/libpmc/pmc.ivybridgexeon.3 | 103 +++++---- lib/libpmc/pmc.sandybridge.3 | 25 +- lib/libpmc/pmc.sandybridgexeon.3 | 120 +++++----- lib/libpmc/pmc.westmere.3 | 4 +- lib/libpmc/pmc.westmereuc.3 | 441 ++++++++++++++++++----------------- 12 files changed, 1024 insertions(+), 910 deletions(-) diff --git a/lib/libpmc/pmc.corei7.3 b/lib/libpmc/pmc.corei7.3 index ec310548d08e..e9e2a6e61784 100644 --- a/lib/libpmc/pmc.corei7.3 +++ b/lib/libpmc/pmc.corei7.3 @@ -93,17 +93,17 @@ Configure the Off-core Response bits. .It Li DMND_DATA_RD Counts the number of demand and DCU prefetch data reads of full and partial cachelines as well as demand data page table entry -cacheline reads. Does not count L2 data read prefetches or -instruction fetches. +cacheline reads. +Does not count L2 data read prefetches or instruction fetches. .It Li DMND_RFO Counts the number of demand and DCU prefetch reads for ownership -(RFO) requests generated by a write to data cacheline. Does not -count L2 RFO. +(RFO) requests generated by a write to data cacheline. +Does not count L2 RFO. .It Li DMND_IFETCH Counts the number of demand and DCU prefetch instruction cacheline -reads. Does not count L2 code read prefetches. -WB -Counts the number of writeback (modified to exclusive) transactions. +reads. +Does not count L2 code read prefetches. +WB Counts the number of writeback (modified to exclusive) transactions. .It Li PF_DATA_RD Counts the number of data cacheline reads generated by L2 prefetchers. .It Li PF_RFO @@ -176,11 +176,11 @@ Core i7 and Xeon 5500 programmable PMCs support the following events: Counts the number of store buffer drains. .It Li STORE_BLOCKS.AT_RET .Pq Event 06H , Umask 04H -Counts number of loads delayed with at-Retirement block code. The following -loads need to be executed at retirement and wait for all senior stores on -the same thread to be drained: load splitting across 4K boundary (page -split), load accessing uncacheable (UC or USWC) memory, load lock, and load -with page table in UC or USWC memory region. +Counts number of loads delayed with at-Retirement block code. +The following loads need to be executed at retirement and wait for all +senior stores on the same thread to be drained: load splitting across +4K boundary (page split), load accessing uncacheable +(UC or USWC) memory, load lock, and load with page table in UC or USWC memory region. .It Li STORE_BLOCKS.L1D_BLOCK .Pq Event 06H , Umask 08H Cacheable loads delayed with L1D block code @@ -220,9 +220,10 @@ ld_lat facility. In conjunction with ld_lat facility .It Li MEM_STORE_RETIRED.DTLB_MISS .Pq Event 0CH , Umask 01H -The event counts the number of retired stores that missed the DTLB. The DTLB -miss is not counted if the store operation causes a fault. Does not counter -prefetches. Counts both primary and secondary misses to the TLB +The event counts the number of retired stores that missed the DTLB. +The DTLB miss is not counted if the store operation causes a fault. +Does not counter prefetches. +Counts both primary and secondary misses to the TLB .It Li UOPS_ISSUED.ANY .Pq Event 0EH , Umask 01H Counts the number of Uops issued by the Register Allocation Table to the @@ -250,18 +251,20 @@ hit modified data in a sibling core residing on the same socket. .It Li MEM_UNCORE_RETIRED.REMOTE_CACHE_LOCAL_HOME_HIT .Pq Event 0FH , Umask 08H Counts number of memory load instructions retired where the memory reference -missed the L1, L2 and L3 caches and HIT in a remote socket's cache. Only -counts locally homed lines. +missed the L1, L2 and L3 caches and HIT in a remote socket's cache. +Only counts locally homed lines. .It Li MEM_UNCORE_RETIRED.REMOTE_DRAM .Pq Event 0FH , Umask 10H Counts number of memory load instructions retired where the memory reference -missed the L1, L2 and L3 caches and was remotely homed. This includes both -DRAM access and HITM in a remote socket's cache for remotely homed lines. +missed the L1, L2 and L3 caches and was remotely homed. +This includes both DRAM access and HITM in a remote socket's cache +for remotely homed lines. .It Li MEM_UNCORE_RETIRED.LOCAL_DRAM .Pq Event 0FH , Umask 20H Counts number of memory load instructions retired where the memory reference missed the L1, L2 and L3 caches and required a local socket memory -reference. This includes locally homed cachelines that were in a modified +reference. +This includes locally homed cachelines that were in a modified state in another socket. .It Li MEM_UNCORE_RETIRED.UNCACHEABLE .Pq Event 0FH , Umask 80H @@ -270,10 +273,10 @@ missed the L1, L2 and L3 caches and to perform I/O. Available only for CPUID signature 06_2EH .It Li FP_COMP_OPS_EXE.X87 .Pq Event 10H , Umask 01H -Counts the number of FP Computational Uops Executed. The number of FADD, -FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer -DIVs, and IDIVs. This event does not distinguish an FADD used in the middle -of a transcendental flow from a separate FADD instruction. +Counts the number of FP Computational Uops Executed. +The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer +DIVs, and IDIVs. +This event does not distinguish an FADD used in the middle of a transcendental flow from a separate FADD instruction. .It Li FP_COMP_OPS_EXE.MMX .Pq Event 10H , Umask 02H Counts number of MMX Uops executed. @@ -322,8 +325,8 @@ Counts number of loads dispatched from the Reservation Station that bypass the Memory Order Buffer. .It Li LOAD_DISPATCH.RS_DELAYED .Pq Event 13H , Umask 02H -Counts the number of delayed RS dispatches at the stage latch. If an RS -dispatch can not bypass to LB, it has another chance to dispatch from the +Counts the number of delayed RS dispatches at the stage latch. +If an RS dispatch can not bypass to LB, it has another chance to dispatch from the one-cycle delayed staging latch before it is written into the LB. .It Li LOAD_DISPATCH.MOB .Pq Event 13H , Umask 04H @@ -335,14 +338,15 @@ Counts all loads dispatched from the Reservation Station. .It Li ARITH.CYCLES_DIV_BUSY .Pq Event 14H , Umask 01H Counts the number of cycles the divider is busy executing divide or square -root operations. The divide can be integer, X87 or Streaming SIMD Extensions -(SSE). The square root operation can be either X87 or SSE. +root operations. +The divide can be integer, X87 or Streaming SIMD Extensions (SSE). +The square root operation can be either X87 or SSE. Set 'edge =1, invert=1, cmask=1' to count the number of divides. Count may be incorrect When SMT is on. .It Li ARITH.MUL .Pq Event 14H , Umask 02H -Counts the number of multiply operations executed. This includes integer as -well as floating point multiply operations but excludes DPPS mul and MPSAD. +Counts the number of multiply operations executed. +This includes integer as well as floating point multiply operations but excludes DPPS mul and MPSAD. Count may be incorrect When SMT is on .It Li INST_QUEUE_WRITES .Pq Event 17H , Umask 01H @@ -350,65 +354,68 @@ Counts the number of instructions written into the instruction queue every cycle. .It Li INST_DECODED.DEC0 .Pq Event 18H , Umask 01H -Counts number of instructions that require decoder 0 to be decoded. Usually, -this means that the instruction maps to more than 1 uop +Counts number of instructions that require decoder 0 to be decoded. +Usually, this means that the instruction maps to more than 1 uop .It Li TWO_UOP_INSTS_DECODED .Pq Event 19H , Umask 01H An instruction that generates two uops was decoded .It Li INST_QUEUE_WRITE_CYCLES .Pq Event 1EH , Umask 01H This event counts the number of cycles during which instructions are written -to the instruction queue. Dividing this counter by the number of -instructions written to the instruction queue (INST_QUEUE_WRITES) yields the -average number of instructions decoded each cycle. If this number is less -than four and the pipe stalls, this indicates that the decoder is failing to +to the instruction queue. +Dividing this counter by the number of instructions written to the +instruction queue (INST_QUEUE_WRITES) yields the average number of +instructions decoded each cycle. +If this number is less than four and the pipe stalls, this indicates that the decoder is failing to decode enough instructions per cycle to sustain the 4-wide pipeline. If SSE* instructions that are 6 bytes or longer arrive one after another, -then front end throughput may limit execution speed. In such case, +then front end throughput may limit execution speed. +In such case, .It Li LSD_OVERFLOW .Pq Event 20H , Umask 01H Counts number of loops that cant stream from the instruction queue. .It Li L2_RQSTS.LD_HIT .Pq Event 24H , Umask 01H -Counts number of loads that hit the L2 cache. L2 loads include both L1D -demand misses as well as L1D prefetches. L2 loads can be rejected for -various reasons. Only non rejected loads are counted. +Counts number of loads that hit the L2 cache. +L2 loads include both L1D demand misses as well as L1D prefetches. +L2 loads can be rejected for various reasons. +Only non rejected loads are counted. .It Li L2_RQSTS.LD_MISS .Pq Event 24H , Umask 02H -Counts the number of loads that miss the L2 cache. L2 loads include both L1D -demand misses as well as L1D prefetches. +Counts the number of loads that miss the L2 cache. +L2 loads include both L1D demand misses as well as L1D prefetches. .It Li L2_RQSTS.LOADS .Pq Event 24H , Umask 03H -Counts all L2 load requests. L2 loads include both L1D demand misses as well -as L1D prefetches. +Counts all L2 load requests. +L2 loads include both L1D demand misses as well as L1D prefetches. .It Li L2_RQSTS.RFO_HIT .Pq Event 24H , Umask 04H -Counts the number of store RFO requests that hit the L2 cache. L2 RFO -requests include both L1D demand RFO misses as well as L1D RFO prefetches. +Counts the number of store RFO requests that hit the L2 cache. +L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches. Count includes WC memory requests, where the data is not fetched but the permission to write the line is required. .It Li L2_RQSTS.RFO_MISS .Pq Event 24H , Umask 08H -Counts the number of store RFO requests that miss the L2 cache. L2 RFO -requests include both L1D demand RFO misses as well as L1D RFO prefetches. +Counts the number of store RFO requests that miss the L2 cache. +L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches. .It Li L2_RQSTS.RFOS .Pq Event 24H , Umask 0CH -Counts all L2 store RFO requests. L2 RFO requests include both L1D demand -RFO misses as well as L1D RFO prefetches. +Counts all L2 store RFO requests. +L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches. .It Li L2_RQSTS.IFETCH_HIT .Pq Event 24H , Umask 10H -Counts number of instruction fetches that hit the L2 cache. L2 instruction -fetches include both L1I demand misses as well as L1I instruction +Counts number of instruction fetches that hit the L2 cache. +L2 instruction fetches include both L1I demand misses as well as L1I instruction prefetches. .It Li L2_RQSTS.IFETCH_MISS .Pq Event 24H , Umask 20H -Counts number of instruction fetches that miss the L2 cache. L2 instruction -fetches include both L1I demand misses as well as L1I instruction +Counts number of instruction fetches that miss the L2 cache. +L2 instruction fetches include both L1I demand misses as well as L1I instruction prefetches. .It Li L2_RQSTS.IFETCHES .Pq Event 24H , Umask 30H -Counts all instruction fetches. L2 instruction fetches include both L1I -demand misses as well as L1I instruction prefetches. +Counts all instruction fetches. +L2 instruction fetches include both L1I demand misses as well as L1I instruction prefetches. .It Li L2_RQSTS.PREFETCH_HIT .Pq Event 24H , Umask 40H Counts L2 prefetch hits for both code and data. @@ -427,27 +434,27 @@ Counts all L2 requests for both code and data. .It Li L2_DATA_RQSTS.DEMAND.I_STATE .Pq Event 26H , Umask 01H Counts number of L2 data demand loads where the cache line to be loaded is -in the I (invalid) state, i.e. a cache miss. L2 demand loads are both L1D -demand misses and L1D prefetches. +in the I (invalid) state, i.e. a cache miss. +L2 demand loads are both L1D demand misses and L1D prefetches. .It Li L2_DATA_RQSTS.DEMAND.S_STATE .Pq Event 26H , Umask 02H Counts number of L2 data demand loads where the cache line to be loaded is -in the S (shared) state. L2 demand loads are both L1D demand misses and L1D -prefetches. +in the S (shared) state. +L2 demand loads are both L1D demand misses and L1D prefetches. .It Li L2_DATA_RQSTS.DEMAND.E_STATE .Pq Event 26H , Umask 04H Counts number of L2 data demand loads where the cache line to be loaded is -in the E (exclusive) state. L2 demand loads are both L1D demand misses and -L1D prefetches. +in the E (exclusive) state. +L2 demand loads are both L1D demand misses and L1D prefetches. .It Li L2_DATA_RQSTS.DEMAND.M_STATE .Pq Event 26H , Umask 08H Counts number of L2 data demand loads where the cache line to be loaded is -in the M (modified) state. L2 demand loads are both L1D demand misses and -L1D prefetches. +in the M (modified) state. +L2 demand loads are both L1D demand misses and L1D prefetches. .It Li L2_DATA_RQSTS.DEMAND.MESI .Pq Event 26H , Umask 0FH -Counts all L2 data demand requests. L2 demand loads are both L1D demand -misses and L1D prefetches. +Counts all L2 data demand requests. +L2 demand loads are both L1D demand misses and L1D prefetches. .It Li L2_DATA_RQSTS.PREFETCH.I_STATE .Pq Event 26H , Umask 10H Counts number of L2 prefetch data loads where the cache line to be loaded is @@ -455,8 +462,9 @@ in the I (invalid) state, i.e. a cache miss. .It Li L2_DATA_RQSTS.PREFETCH.S_STATE .Pq Event 26H , Umask 20H Counts number of L2 prefetch data loads where the cache line to be loaded is -in the S (shared) state. A prefetch RFO will miss on an S state line, while -a prefetch read will hit on an S state line. +in the S (shared) state. +A prefetch RFO will miss on an S state line, while a prefetch read will +hit on an S state line. .It Li L2_DATA_RQSTS.PREFETCH.E_STATE .Pq Event 26H , Umask 40H Counts number of L2 prefetch data loads where the cache line to be loaded is @@ -474,29 +482,31 @@ Counts all L2 data requests. .It Li L2_WRITE.RFO.I_STATE .Pq Event 27H , Umask 01H Counts number of L2 demand store RFO requests where the cache line to be -loaded is in the I (invalid) state, i.e, a cache miss. The L1D prefetcher -does not issue a RFO prefetch. +loaded is in the I (invalid) state, i.e, a cache miss. +The L1D prefetcher does not issue a RFO prefetch. This is a demand RFO request .It Li L2_WRITE.RFO.S_STATE .Pq Event 27H , Umask 02H Counts number of L2 store RFO requests where the cache line to be loaded is -in the S (shared) state. The L1D prefetcher does not issue a RFO prefetch,. +in the S (shared) state. +The L1D prefetcher does not issue a RFO prefetch. This is a demand RFO request .It Li L2_WRITE.RFO.M_STATE .Pq Event 27H , Umask 08H Counts number of L2 store RFO requests where the cache line to be loaded is -in the M (modified) state. The L1D prefetcher does not issue a RFO prefetch. +in the M (modified) state. +The L1D prefetcher does not issue a RFO prefetch. This is a demand RFO request .It Li L2_WRITE.RFO.HIT .Pq Event 27H , Umask 0EH Counts number of L2 store RFO requests where the cache line to be loaded is -in either the S, E or M states. The L1D prefetcher does not issue a RFO -prefetch. +in either the S, E or M states. +The L1D prefetcher does not issue a RFO prefetch. This is a demand RFO request .It Li L2_WRITE.RFO.MESI .Pq Event 27H , Umask 0FH -Counts all L2 store RFO requests.The L1D prefetcher does not issue a RFO -prefetch. +Counts all L2 store RFO requests. +The L1D prefetcher does not issue a RFO prefetch. This is a demand RFO request .It Li L2_WRITE.LOCK.I_STATE .Pq Event 27H , Umask 10H @@ -543,25 +553,26 @@ Counts all L1 writebacks to the L2. .It Li L3_LAT_CACHE.REFERENCE .Pq Event 2EH , Umask 4FH This event counts requests originating from the core that reference a cache -line in the last level cache. The event count includes speculative traffic -but excludes cache line fills due to a L2 hardware-prefetch. Because cache -hierarchy, cache sizes and other implementation-specific characteristics; -value comparison to estimate performance differences is not recommended. +line in the last level cache. +The event count includes speculative traffic but excludes cache line fills +due to a L2 hardware-prefetch. +Because cache hierarchy, cache sizes and other implementation-specific +characteristics; value comparison to estimate performance differences is not recommended. see Table A-1 .It Li L3_LAT_CACHE.MISS .Pq Event 2EH , Umask 41H This event counts each cache miss condition for references to the last level -cache. The event count may include speculative traffic but excludes cache -line fills due to L2 hardware-prefetches. Because cache hierarchy, cache -sizes and other implementation-specific characteristics; value comparison to -estimate performance differences is not recommended. +cache. +The event count may include speculative traffic but excludes cache +line fills due to L2 hardware-prefetches. +Because cache hierarchy, cache sizes and other implementation-specific +characteristics; value comparison to estimate performance differences is not recommended. see Table A-1 .It Li CPU_CLK_UNHALTED.THREAD_P .Pq Event 3CH , Umask 00H Counts the number of thread cycles while the thread is not in a halt state. -The thread enters the halt state when it is running the HLT instruction. The -core frequency may change from time to time due to power or thermal -throttling. +The thread enters the halt state when it is running the HLT instruction. +The core frequency may change from time to time due to power or thermal throttling. see Table A-1 .It Li CPU_CLK_UNHALTED.REF_P .Pq Event 3CH , Umask 01H @@ -609,10 +620,10 @@ Counter 0, 1 only .It Li L1D_CACHE_LOCK.HIT .Pq Event 42H , Umask 01H Counts retired load locks that hit in the L1 data cache or hit in an already -allocated fill buffer. The lock portion of the load lock transaction must -hit in the L1D. -The initial load will pull the lock into the L1 data cache. Counter 0, 1 -only +allocated fill buffer. +The lock portion of the load lock transaction must hit in the L1D. +The initial load will pull the lock into the L1 data cache. +Counter 0, 1 only .It Li L1D_CACHE_LOCK.S_STATE .Pq Event 42H , Umask 02H Counts L1 data cache retired load locks that hit the target cache line in @@ -631,10 +642,10 @@ Counter 0, 1 only .It Li L1D_ALL_REF.ANY .Pq Event 43H , Umask 01H Counts all references (uncached, speculated and retired) to the L1 data -cache, including all loads and stores with any memory types. The event -counts memory accesses only when they are actually performed. For example, a -load blocked by unknown store address and later performed is only counted -once. +cache, including all loads and stores with any memory types. +The event counts memory accesses only when they are actually performed. +For example, a load blocked by unknown store address and later performed +is only counted once. The event does not include non- memory accesses, such as I/O accesses. Counter 0, 1 only .It Li L1D_ALL_REF.CACHEABLE @@ -650,8 +661,8 @@ Counts the number of misses in the STLB which causes a page walk. Counts number of misses in the STLB which resulted in a completed page walk. .It Li DTLB_MISSES.STLB_HIT .Pq Event 49H , Umask 10H -Counts the number of DTLB first level misses that hit in the second level -TLB. This event is only relevant if the core contains multiple DTLB levels. +Counts the number of DTLB first level misses that hit in the second level TLB. +This event is only relevant if the core contains multiple DTLB levels. .It Li DTLB_MISSES.PDE_MISS .Pq Event 49H , Umask 20H Number of DTLB misses caused by low part of address, includes references to 2M pages because 2M pages do not use the PDE. @@ -669,17 +680,18 @@ Counts number of hardware prefetch requests dispatched out of the prefetch FIFO. .It Li L1D_PREFETCH.MISS .Pq Event 4EH , Umask 02H -Counts number of hardware prefetch requests that miss the L1D. There are two -prefetchers in the L1D. A streamer, which predicts lines sequentially after -this one should be fetched, and the IP prefetcher that remembers access -patterns for the current instruction. The streamer prefetcher stops on an -L1D hit, while the IP prefetcher does not. +Counts number of hardware prefetch requests that miss the L1D. +There are two prefetchers in the L1D. +A streamer, which predicts lines sequentially after this one should be fetched, +and the IP prefetcher that remembers access patterns for the current instruction. +The streamer prefetcher stops on an L1D hit, while the IP prefetcher does not. .It Li L1D_PREFETCH.TRIGGERS .Pq Event 4EH , Umask 04H Counts number of prefetch requests triggered by the Finite State Machine and -pushed into the prefetch FIFO. Some of the prefetch requests are dropped due -to overwrites or competition between the IP index prefetcher and streamer -prefetcher. The prefetch FIFO contains 4 entries. +pushed into the prefetch FIFO. +Some of the prefetch requests are dropped due to overwrites or competition between +the IP index prefetcher and streamer prefetcher. +The prefetch FIFO contains 4 entries. .It Li L1D.REPL .Pq Event 51H , Umask 01H Counts the number of lines brought into the L1 data cache. @@ -708,12 +720,13 @@ Counts the number of cacheable load lock speculated or retired instructions accepted into the fill buffer. .It Li CACHE_LOCK_CYCLES.L1D_L2 .Pq Event 63H , Umask 01H -Cycle count during which the L1D and L2 are locked. A lock is asserted when -there is a locked memory access, due to uncacheable memory, a locked +Cycle count during which the L1D and L2 are locked. +A lock is asserted when there is a locked memory access, due to uncacheable memory, a locked operation that spans two cache lines, or a page walk from an uncacheable page table. -Counter 0, 1 only. L1D and L2 locks have a very high performance penalty and -it is highly recommended to avoid such accesses. +Counter 0, 1 only. +L1D and L2 locks have a very high performance penalty and it is highly recommended to +avoid such accesses. .It Li CACHE_LOCK_CYCLES.L1D .Pq Event 63H , Umask 02H Counts the number of cycles that cacheline in the L1 data cache unit is @@ -727,10 +740,11 @@ Counts the number of completed I/O transactions. Counts all instruction fetches that hit the L1 instruction cache. .It Li L1I.MISSES .Pq Event 80H , Umask 02H -Counts all instruction fetches that miss the L1I cache. This includes -instruction cache misses, streaming buffer misses, victim cache misses and -uncacheable fetches. An instruction fetch miss is counted only once and not -once for every cycle it is outstanding. +Counts all instruction fetches that miss the L1I cache. +This includes instruction cache misses, streaming buffer misses, victim cache misses and +uncacheable fetches. +An instruction fetch miss is counted only once and not once for every cycle +it is outstanding. .It Li L1I.READS .Pq Event 80H , Umask 03H Counts all instruction fetches, including uncacheable fetches that bypass @@ -803,10 +817,10 @@ Counts all near call branches executed, but not necessarily retired. Counts taken near branches executed, but not necessarily retired. .It Li BR_INST_EXEC.ANY .Pq Event 88H , Umask 7FH -Counts all near executed branches (not necessarily retired). This includes -only instructions and not micro-op branches. Frequent branching is not -necessarily a major performance issue. However frequent branch -mispredictions may be a problem. +Counts all near executed branches (not necessarily retired). +This includes only instructions and not micro-op branches. +Frequent branching is not necessarily a major performance issue. +However frequent branch mispredictions may be a problem. .It Li BR_MISP_EXEC.COND .Pq Event 89H , Umask 01H Counts the number of mispredicted conditional near branch instructions @@ -847,10 +861,10 @@ Counts the number of mispredicted near branch instructions that were executed, but not necessarily retired. .It Li RESOURCE_STALLS.ANY .Pq Event A2H , Umask 01H -Counts the number of Allocator resource related stalls. Includes register -renaming buffer entries, memory buffer entries. In addition to resource -related stalls, this event counts some other events. Includes stalls arising -during branch misprediction recovery, such as if retirement of the +Counts the number of Allocator resource related stalls. +Includes register renaming buffer entries, memory buffer entries. +In addition to resource related stalls, this event counts some other events. +Includes stalls arising during branch misprediction recovery, such as if retirement of the mispredicted branch is delayed and stalls arising while store buffer is draining from synchronizing operations. Does not include stalls due to SuperQ (off core) queue full, too many cache @@ -861,8 +875,8 @@ Counts the cycles of stall due to lack of load buffer for load operation. .It Li RESOURCE_STALLS.RS_FULL .Pq Event A2H , Umask 04H This event counts the number of cycles when the number of instructions in -the pipeline waiting for execution reaches the limit the processor can -handle. A high count of this event indicates that there are long latency +the pipeline waiting for execution reaches the limit the processor can handle. +A high count of this event indicates that there are long latency operations in the pipe (possibly load and store operations that miss the L2 cache, or instructions dependent upon instructions further down the pipeline that have yet to retire. @@ -872,8 +886,8 @@ start execution. .Pq Event A2H , Umask 08H This event counts the number of cycles that a resource related stall will occur due to the number of store instructions reaching the limit of the -pipeline, (i.e. all store buffers are used). The stall ends when a store -instruction commits its data to the cache or memory. +pipeline, (i.e. all store buffers are used). +The stall ends when a store instruction commits its data to the cache or memory. .It Li RESOURCE_STALLS.ROB_FULL .Pq Event A2H , Umask 10H Counts the cycles of stall due to re- order buffer full. @@ -884,7 +898,8 @@ floating-point unit (FPU) control word. .It Li RESOURCE_STALLS.MXCSR .Pq Event A2H , Umask 40H Stalls due to the MXCSR register rename occurring to close to a previous -MXCSR rename. The MXCSR provides control and status for the MMX registers. +MXCSR rename. +The MXCSR provides control and status for the MMX registers. .It Li RESOURCE_STALLS.OTHER .Pq Event A2H , Umask 80H Counts the number of cycles while execution was stalled due to other @@ -895,14 +910,15 @@ Counts the number of instructions decoded that are macro-fused but not necessarily executed or retired. .It Li BACLEAR_FORCE_IQ .Pq Event A7H , Umask 01H -Counts number of times a BACLEAR was forced by the Instruction Queue. The IQ -is also responsible for providing conditional branch prediction direction +Counts number of times a BACLEAR was forced by the Instruction Queue. +The IQ is also responsible for providing conditional branch prediction direction based on a static scheme and dynamic data provided by the L2 Branch -Prediction Unit. If the conditional branch target is not found in the Target -Array and the IQ predicts that the branch is taken, then the IQ will force -the Branch Address Calculator to issue a BACLEAR. Each BACLEAR asserted by -the BAC generates approximately an 8 cycle bubble in the instruction fetch -pipeline. +Prediction Unit. +If the conditional branch target is not found in the Target Array and the IQ +predicts that the branch is taken, then the IQ will force +the Branch Address Calculator to issue a BACLEAR. +Each BACLEAR asserted by the BAC generates approximately an 8 cycle bubble +in the instruction fetch pipeline. .It Li LSD.UOPS .Pq Event A8H , Umask 01H Counts the number of micro-ops delivered by loop stream detector @@ -915,30 +931,32 @@ Counts the number of ITLB flushes Counts number of L1D writebacks to the uncore. .It Li UOPS_EXECUTED.PORT0 .Pq Event B1H , Umask 01H -Counts number of Uops executed that were issued on port 0. Port 0 handles -integer arithmetic, SIMD and FP add Uops. +Counts number of Uops executed that were issued on port 0. +Port 0 handles integer arithmetic, SIMD and FP add Uops. .It Li UOPS_EXECUTED.PORT1 .Pq Event B1H , Umask 02H -Counts number of Uops executed that were issued on port 1. Port 1 handles -integer arithmetic, SIMD, integer shift, FP multiply and FP divide Uops. +Counts number of Uops executed that were issued on port 1. +Port 1 handles integer arithmetic, SIMD, integer shift, FP multiply and FP divide Uops. .It Li UOPS_EXECUTED.PORT2_CORE .Pq Event B1H , Umask 04H -Counts number of Uops executed that were issued on port 2. Port 2 handles -the load Uops. This is a core count only and can not be collected per -thread. +Counts number of Uops executed that were issued on port 2. +Port 2 handles the load Uops. +This is a core count only and can not be collected per thread. .It Li UOPS_EXECUTED.PORT3_CORE .Pq Event B1H , Umask 08H -Counts number of Uops executed that were issued on port 3. Port 3 handles -store Uops. This is a core count only and can not be collected per thread. +Counts number of Uops executed that were issued on port 3. +Port 3 handles store Uops. +This is a core count only and can not be collected per thread. .It Li UOPS_EXECUTED.PORT4_CORE .Pq Event B1H , Umask 10H -Counts number of Uops executed that where issued on port 4. Port 4 handles -the value to be stored for the store Uops issued on port 3. This is a core -count only and can not be collected per thread. +Counts number of Uops executed that where issued on port 4. +Port 4 handles the value to be stored for the store Uops issued on port 3. +This is a core count only and can not be collected per thread. .It Li UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5 .Pq Event B1H , Umask 1FH Counts cycles when the Uops executed were issued from any ports except port -5. Use Cmask=1 for active cycles; Cmask=0 for weighted cycles; Use CMask=1, +5. +Use Cmask=1 for active cycles; Cmask=0 for weighted cycles; Use CMask=1, Invert=1 to count P0-4 stalled cycles Use Cmask=1, Edge=1, Invert=1 to count P0-4 stalls. .It Li UOPS_EXECUTED.PORT5 @@ -946,8 +964,8 @@ P0-4 stalls. Counts number of Uops executed that where issued on port 5. .It Li UOPS_EXECUTED.CORE_ACTIVE_CYCLES .Pq Event B1H , Umask 3FH -Counts cycles when the Uops are executing. Use Cmask=1 for active cycles; -Cmask=0 for weighted cycles; Use CMask=1, Invert=1 to count P0-4 stalled +Counts cycles when the Uops are executing. +Use Cmask=1 for active cycles; Cmask=0 for weighted cycles; Use CMask=1, Invert=1 to count P0-4 stalled cycles Use Cmask=1, Edge=1, Invert=1 to count P0-4 stalls. .It Li UOPS_EXECUTED.PORT015 .Pq Event B1H , Umask 40H @@ -986,7 +1004,8 @@ Requires programming MSR 01A7H See Table A-1 Notes: INST_RETIRED.ANY is counted by a designated fixed counter. INST_RETIRED.ANY_P is counted by a programmable counter and is an -architectural performance event. Event is supported if CPUID.A.EBX[1] = 0. +architectural performance event. +Event is supported if CPUID.A.EBX[1] = 0. Counting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions. .It Li INST_RETIRED.X87 @@ -1001,10 +1020,10 @@ instructions. .It Li UOPS_RETIRED.ANY .Pq Event C2H , Umask 01H Counts the number of micro-ops retired, (macro-fused=1, micro- fused=2, -others=1; maximum count of 8 per cycle). Most instructions are composed of -one or two micro-ops. Some instructions are decoded into longer sequences -such as repeat instructions, floating point transcendental instructions, and -assists. +others=1; maximum count of 8 per cycle). +Most instructions are composed of one or two micro-ops. +Some instructions are decoded into longer sequences such as repeat instructions, +floating point transcendental instructions, and assists. Use cmask=1 and invert to count active cycles or stalled cycles .It Li UOPS_RETIRED.RETIRE_SLOTS .Pq Event C2H , Umask 02H @@ -1022,7 +1041,8 @@ Counts the number of machine clears due to memory order conflicts. .Pq Event C3H , Umask 04H Counts the number of times that a program writes to a code section. Self-modifying code causes a sever penalty in all Intel 64 and IA-32 -processors. The modified cache line is written back to the L2 and L3caches. +processors. +The modified cache line is written back to the L2 and L3caches. .It Li BR_INST_RETIRED.ALL_BRANCHES .Pq Event C4H , Umask 00H See Table A-1 @@ -1072,24 +1092,25 @@ Counts number of retired loads that hit their own, unshared lines in the L3 cache. .It Li MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM .Pq Event CBH , Umask 08H -Counts number of retired loads that hit in a sibling core's L2 (on die -core). Since the L3 is inclusive of all cores on the package, this is an L3 -hit. This counts both clean or modified hits. +Counts number of retired loads that hit in a sibling core's L2 (on die core). +Since the L3 is inclusive of all cores on the package, this is an L3 hit. +This counts both clean or modified hits. .It Li MEM_LOAD_RETIRED.L3_MISS .Pq Event CBH , Umask 10H -Counts number of retired loads that miss the L3 cache. The load was -satisfied by a remote socket, local memory or an IOH. +Counts number of retired loads that miss the L3 cache. +The load was satisfied by a remote socket, local memory or an IOH. .It Li MEM_LOAD_RETIRED.HIT_LFB .Pq Event CBH , Umask 40H Counts number of retired loads that miss the L1D and the address is located -in an allocated line fill buffer and will soon be committed to cache. This -is counting secondary L1D misses. +in an allocated line fill buffer and will soon be committed to cache. +This is counting secondary L1D misses. .It Li MEM_LOAD_RETIRED.DTLB_MISS .Pq Event CBH , Umask 80H -Counts the number of retired loads that missed the DTLB. The DTLB miss is -not counted if the load operation causes a fault. This event counts loads -from cacheable memory only. The event does not count loads by software -prefetches. Counts both primary and secondary misses to the TLB. +Counts the number of retired loads that missed the DTLB. +The DTLB miss is not counted if the load operation causes a fault. +This event counts loads from cacheable memory only. +The event does not count loads by software prefetches. +Counts both primary and secondary misses to the TLB. .It Li FP_MMX_TRANS.TO_FP .Pq Event CCH , Umask 01H Counts the first floating-point instruction following any MMX instruction. @@ -1097,29 +1118,30 @@ You can use this event to estimate the penalties for the transitions between floating-point and MMX technology states. .It Li FP_MMX_TRANS.TO_MMX .Pq Event CCH , Umask 02H -Counts the first MMX instruction following a floating-point instruction. You -can use this event to estimate the penalties for the transitions between +Counts the first MMX instruction following a floating-point instruction. +You can use this event to estimate the penalties for the transitions between floating-point and MMX technology states. .It Li FP_MMX_TRANS.ANY .Pq Event CCH , Umask 03H Counts all transitions from floating point to MMX instructions and from MMX -instructions to floating point instructions. You can use this event to -estimate the penalties for the transitions between floating-point and MMX -technology states. +instructions to floating point instructions. +You can use this event to estimate the penalties for the transitions between +floating-point and MMX technology states. .It Li MACRO_INSTS.DECODED .Pq Event D0H , Umask 01H Counts the number of instructions decoded, (but not necessarily executed or retired). .It Li UOPS_DECODED.MS .Pq Event D1H , Umask 02H -Counts the number of Uops decoded by the Microcode Sequencer, MS. The MS -delivers uops when the instruction is more than 4 uops long or a microcode +Counts the number of Uops decoded by the Microcode Sequencer, MS. +The MS delivers uops when the instruction is more than 4 uops long or a microcode assist is occurring. .It Li UOPS_DECODED.ESP_FOLDING .Pq Event D1H , Umask 04H Counts number of stack pointer (ESP) instructions decoded: push , pop , call -, ret, etc. ESP instructions do not generate a Uop to increment or decrement -ESP. Instead, they update an ESP_Offset register that keeps track of the +, ret, etc. +ESP instructions do not generate a Uop to increment or decrement ESP. +Instead, they update an ESP_Offset register that keeps track of the delta to the current value of the ESP register. .It Li UOPS_DECODED.ESP_SYNC .Pq Event D1H , Umask 08H @@ -1129,8 +1151,8 @@ value of the ESP register. .It Li RAT_STALLS.FLAGS .Pq Event D2H , Umask 01H Counts the number of cycles during which execution stalled due to several -reasons, one of which is a partial flag register stall. A partial register -stall may occur when two conditions are met: 1) an instruction modifies +reasons, one of which is a partial flag register stall. +A partial register stall may occur when two conditions are met: 1) an instruction modifies some, but not all, of the flags in the flag register and 2) the next instruction, which depends on flags, depends on flags that were not modified by this instruction. @@ -1142,30 +1164,33 @@ was partially written by previous instruction. .It Li RAT_STALLS.ROB_READ_PORT .Pq Event D2H , Umask 04H Counts the number of cycles when ROB read port stalls occurred, which did -not allow new micro-ops to enter the out-of-order pipeline. Note that, at -this stage in the pipeline, additional stalls may occur at the same cycle -and prevent the stalled micro-ops from entering the pipe. In such a case, -micro-ops retry entering the execution pipe in the next cycle and the -ROB-read port stall is counted again. +not allow new micro-ops to enter the out-of-order pipeline. +Note that, at this stage in the pipeline, additional stalls may occur at +the same cycle and prevent the stalled micro-ops from entering the pipe. +In such a case, micro-ops retry entering the execution pipe in the next +cycle and the ROB-read port stall is counted again. .It Li RAT_STALLS.SCOREBOARD .Pq Event D2H , Umask 08H Counts the cycles where we stall due to microarchitecturally required -serialization. Microcode scoreboarding stalls. +serialization. +Microcode scoreboarding stalls. .It Li RAT_STALLS.ANY .Pq Event D2H , Umask 0FH Counts all Register Allocation Table stall cycles due to: Cycles when ROB read port stalls occurred, which did not allow new micro-ops to enter the -execution pipe. Cycles when partial register stalls occurred Cycles when -flag stalls occurred Cycles floating-point unit (FPU) status word stalls -occurred. To count each of these conditions separately use the events: +execution pipe. +Cycles when partial register stalls occurred Cycles when flag stalls occurred +Cycles floating-point unit (FPU) status word stalls occurred. +To count each of these conditions separately use the events: RAT_STALLS.ROB_READ_PORT, RAT_STALLS.PARTIAL, RAT_STALLS.FLAGS, and RAT_STALLS.FPSW. .It Li SEG_RENAME_STALLS .Pq Event D4H , Umask 01H Counts the number of stall cycles due to the lack of renaming resources for -the ES, DS, FS, and GS segment registers. If a segment is renamed but not -retired and a second update to the same segment occurs, a stall occurs in -the front-end of the pipeline until the renamed segment retires. +the ES, DS, FS, and GS segment registers. +If a segment is renamed but not retired and a second update to the same +segment occurs, a stall occurs in the front-end of the pipeline until the +renamed segment retires. .It Li ES_REG_RENAMES .Pq Event D5H , Umask 01H Counts the number of times the ES segment register is renamed. @@ -1183,17 +1208,19 @@ or return branch. .Pq Event E6H , Umask 01H Counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is -corrected by the Branch Address Calculator at the front end. This can occur -if the code has many branches such that they cannot be consumed by the BPU. +corrected by the Branch Address Calculator at the front end. +This can occur if the code has many branches such that they cannot be +consumed by the BPU. Each BACLEAR asserted by the BAC generates approximately an 8 cycle bubble -in the instruction fetch pipeline. The effect on total execution time -depends on the surrounding code. +in the instruction fetch pipeline. +The effect on total execution time depends on the surrounding code. .It Li BACLEAR.BAD_TARGET .Pq Event E6H , Umask 02H Counts number of Branch Address Calculator clears (BACLEAR) asserted due to conditional branch instructions in which there was a target hit but the -direction was wrong. Each BACLEAR asserted by the BAC generates -approximately an 8 cycle bubble in the instruction fetch pipeline. +direction was wrong. +Each BACLEAR asserted by the BAC generates approximately an 8 cycle bubble in +the instruction fetch pipeline. .It Li BPU_CLEARS.EARLY .Pq Event E8H , Umask 01H Counts early (normal) Branch Prediction Unit clears: BPU predicted a taken @@ -1201,8 +1228,8 @@ branch after incorrectly assuming that it was not taken. The BPU clear leads to 2 cycle bubble in the Front End. .It Li BPU_CLEARS.LATE .Pq Event E8H , Umask 02H -Counts late Branch Prediction Unit clears due to Most Recently Used -conflicts. The PBU clear leads to a 3 cycle bubble in the Front End. +Counts late Branch Prediction Unit clears due to Most Recently Used conflicts. +The PBU clear leads to a 3 cycle bubble in the Front End. .It Li L2_TRANSACTIONS.LOAD .Pq Event F0H , Umask 01H Counts L2 load operations due to HW prefetch or demand loads. @@ -1259,12 +1286,13 @@ Counts all L2 cache lines evicted for any reason. Counts the number of SQ lock splits across a cache line. .It Li SQ_FULL_STALL_CYCLES .Pq Event F6H , Umask 01H -Counts cycles the Super Queue is full. Neither of the threads on this core -will be able to access the uncore. +Counts cycles the Super Queue is full. +Neither of the threads on this core will be able to access the uncore. .It Li FP_ASSIST.ALL .Pq Event F7H , Umask 01H Counts the number of floating point operations executed that required -micro-code assist intervention. Assists are required in the following cases: +micro-code assist intervention. +Assists are required in the following cases: SSE instructions, (Denormal input when the DAZ flag is off or Underflow result when the FTZ flag is off): x87 instructions, (NaN or denormal are loaded to a register or used as input from memory, Division by 0 or @@ -1361,8 +1389,8 @@ Number of cycles interrupts are pending and masked .It Li HW_INT.CYCLES_PENDING_AND_MASKED .Pq Event 04H , Umask 04H Counts number of L2 store RFO requests where the cache line to be loaded is -in the E (exclusive) state. The L1D prefetcher does not issue a RFO -prefetch. +in the E (exclusive) state. +The L1D prefetcher does not issue a RFO prefetch. This is a demand RFO request .It Li HW_INT.CYCLES_PENDING_AND_MASKED .Pq Event 27H , Umask 04H @@ -1403,34 +1431,34 @@ Counts number of SSE non temporal stores Counts store fence cycles .It Li EPT.EPDE_MISS .Pq Event 4FH , Umask 02H -Counts Extended Page Directory Entry misses. The Extended Page Directory -cache is used by Virtual Machine operating systems while the guest operating -systems use the standard TLB caches. +Counts Extended Page Directory Entry misses. +The Extended Page Directory cache is used by Virtual Machine operating +systems while the guest operating systems use the standard TLB caches. .It Li EPT.EPDPE_HIT .Pq Event 4FH , Umask 04H Counts Extended Page Directory Pointer Entry hits. .It Li EPT.EPDPE_MISS .Pq Event 4FH , Umask 08H -Counts Extended Page Directory Pointer Entry misses. T +Counts Extended Page Directory Pointer Entry misses. .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA .Pq Event 60H , Umask 01H -Counts weighted cycles of offcore demand data read requests. Does not -include L2 prefetch requests. +Counts weighted cycles of offcore demand data read requests. +Does not include L2 prefetch requests. counter 0 .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE .Pq Event 60H , Umask 02H -Counts weighted cycles of offcore demand code read requests. Does not -include L2 prefetch requests. +Counts weighted cycles of offcore demand code read requests. +Does not include L2 prefetch requests. counter 0 .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO .Pq Event 60H , Umask 04H -Counts weighted cycles of offcore demand RFO requests. Does not include L2 -prefetch requests. +Counts weighted cycles of offcore demand RFO requests. +Does not include L2 prefetch requests. counter 0 .It Li OFFCORE_REQUESTS_OUTSTANDING.ANY.READ .Pq Event 60H , Umask 08H -Counts weighted cycles of offcore read requests of any kind. Include L2 -prefetch requests. +Counts weighted cycles of offcore read requests of any kind. +Include L2 prefetch requests. counter 0 .It Li IFU_IVC.FULL .Pq Event 81H , Umask 01H @@ -1463,22 +1491,24 @@ translation was missed. Counts number of completed large page walks due to misses in the STLB. .It Li ITLB_MISSES.LARGE_WALK_COMPLETED .Pq Event 01H , Umask 80H -Counts number of offcore demand data read requests. Does not count L2 -prefetch requests. +Counts number of offcore demand data read requests. +Does not count L2 prefetch requests. .It Li OFFCORE_REQUESTS.DEMAND.READ_CODE .Pq Event B0H , Umask 02H -Counts number of offcore demand code read requests. Does not count L2 -prefetch requests. +Counts number of offcore demand code read requests. +Does not count L2 prefetch requests. .It Li OFFCORE_REQUESTS.DEMAND.RFO .Pq Event B0H , Umask 04H -Counts number of offcore demand RFO requests. Does not count L2 prefetch -requests. +Counts number of offcore demand RFO requests. +Does not count L2 prefetch requests. .It Li OFFCORE_REQUESTS.ANY.READ .Pq Event B0H , Umask 08H -Counts number of offcore read requests. Includes L2 prefetch requests. +Counts number of offcore read requests. +Includes L2 prefetch requests. .It Li OFFCORE_REQUESTS.ANY.RFO .Pq Event B0H , Umask 10H -Counts number of offcore RFO requests. Includes L2 prefetch requests. +Counts number of offcore RFO requests. +Includes L2 prefetch requests. .It Li OFFCORE_REQUESTS.UNCACHED_MEM .Pq Event B0H , Umask 20H Counts number of offcore uncached memory requests. @@ -1487,23 +1517,23 @@ Counts number of offcore uncached memory requests. Counts all offcore requests. .It Li SNOOPQ_REQUESTS_OUTSTANDING.DATA .Pq Event B3H , Umask 01H -Counts weighted cycles of snoopq requests for data. Counter 0 only -Use cmask=1 to count cycles not empty. +Counts weighted cycles of snoopq requests for data. +Counter 0 only Use cmask=1 to count cycles not empty. .It Li SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE .Pq Event B3H , Umask 02H -Counts weighted cycles of snoopq invalidate requests. Counter 0 only -Use cmask=1 to count cycles not empty. +Counts weighted cycles of snoopq invalidate requests. +Counter 0 only Use cmask=1 to count cycles not empty. .It Li SNOOPQ_REQUESTS_OUTSTANDING.CODE .Pq Event B3H , Umask 04H -Counts weighted cycles of snoopq requests for code. Counter 0 only -Use cmask=1 to count cycles not empty. +Counts weighted cycles of snoopq requests for code. +Counter 0 only Use cmask=1 to count cycles not empty. .It Li SNOOPQ_REQUESTS_OUTSTANDING.CODE .Pq Event BAH , Umask 04H Counts number of TPR reads .It Li PIC_ACCESSES.TPR_WRITES .Pq Event BAH , Umask 02H -Counts number of TPR writes -one or two micro-ops. Some instructions are decoded into longer sequences +Counts number of TPR writes one or two micro-ops. +Some instructions are decoded into longer sequences .It Li MACHINE_CLEARS.FUSION_ASSIST .Pq Event C3H , Umask 10H Counts the number of macro-fusion assists diff --git a/lib/libpmc/pmc.corei7uc.3 b/lib/libpmc/pmc.corei7uc.3 index 3bcda1c7b499..1f49222ceda6 100644 --- a/lib/libpmc/pmc.corei7uc.3 +++ b/lib/libpmc/pmc.corei7uc.3 @@ -115,8 +115,8 @@ Uncore cycles Global Queue read tracker is full. Uncore cycles Global Queue write tracker is full. .It Li GQ_CYCLES_FULL.PEER_PROBE_TRACKER *** 2807 LINES SKIPPED ***
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