Date: Tue, 2 Jul 2013 04:27:16 +0000 (UTC) From: Navdeep Parhar <np@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-9@freebsd.org Subject: svn commit: r252495 - in stable/9: share/man/man4 sys/dev/cxgb sys/dev/cxgbe sys/dev/cxgbe/common sys/dev/cxgbe/firmware sys/dev/cxgbe/tom sys/modules/cxgbe sys/modules/cxgbe/firmware sys/modules/c... Message-ID: <201307020427.r624RGHP086501@svn.freebsd.org>
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Author: np Date: Tue Jul 2 04:27:16 2013 New Revision: 252495 URL: http://svnweb.freebsd.org/changeset/base/252495 Log: MFC all cxgbe(4) changes missing from stable/9: r248925, r249368, r249370, r249376, r249382, r249383, r249385, r249391, r249392, r249393, r249627, r249629, r250090, r250092, r250093, r250117, r250218, r250221, r250614, r251213, r251317, r251358, r251434, r251518, r251638, r252312, r252469, r252470, r250697(kib). r248925: Support for Chelsio's 40G Terminator 5 (aka T5) ASIC. ... r249368: Set and display the IP fragment bit correctly when dealing with the filter mode. r249370: cxgbe(4): Ensure that the MOD_LOAD handler runs before either t4nex or t5nex attach to their devices. r249376: - Explain clearly why a different firmware is being installed (if/when it is being installed). Improve other error messages while here. - Select special FPGA specific configuration profile when appropriate. r249382: There is no need for elaborate queries and error checking when trying to set FW4MSG_ENCAP. r249383: Get rid of a couple of stray \n's. r249385: cxgbe/tom: Slight simplification of code that calculates options2. r249391: Auto-reduce the holdoff timers that are greater than the maximum value allowed by the hardware. r249392: Cosmetic change (s/wrwc/wcwr/;s/WRWC/WCWR/). r249393: Add pciids of the T5 based cards. The ones that I haven't tested with cxgbe(4) are disabled for now. This will change. r249627: cxgbe/tom: Update the CLIP table on the chip when there are changes to the list of IPv6 addresses on the system. The table is used for TOE+IPv6 only. r249629: cxgbe(4): Refuse to install T5 firmwares on a T4 card (and vice versa). r250090: cxgbe(4): Some updates to shared code. r250092: - Provide accurate ifmedia information so that 40G ports/transceivers are displayed properly in ifconfig, etc. - Use the same number of tx and rx queues for a 40G port as for a 10G port. r250093: Attach to the T580 (2 x 40G) card. r250117: Fix DDP breakage introduced in r248925. Bitwise OR has higher precedence than ternary conditional. r250218: cxgbe/tom: Do not use M_PROTO1 to mark rx zero-copy mbufs as special. All the M_PROTOn flags are clobbered when an mbuf is appended to the socket buffer. r250221: cxgbe: Switch to a better way to install firmware. r250614: Deal correctly with 40G ports that don't have any transceiver plugged in. Do not claim that they have unknown tranceivers. r251213: cxgbe(4): Some more debug sysctls. These work on both T4 and T5 based cards. r251317: cxgbe(4): t4fw_cfg must be explicitly loaded if the driver is being loaded via loader.conf. r251358: cxgbe(4): Provide accurate hit count for filters on T5 cards. The location within the TCB and the size have both changed. r251434: cxgbe(4): Never install a firmware if hw.cxgbe.fw_install is 0. r251518: cxgbe/tom: Fix bad signed/unsigned mixup in the stid allocator. This fixes a panic when allocating a mixture of IPv6 and IPv4 stids. r251638: cxgbe/tom: Allow caller to select the queue (control or data) used to send the CPL_SET_TCB_FIELD request in t4_set_tcb_field(). r252312: Update T5 register ranges. This is so that regdump skips over registers with read side-effects. r252469: Add a sysctl to get the number of filters available. sysctl dev.t4nex.<N>.nfilters sysctl dev.t5nex.<N>.nfilters r252470: Count the number of hits for a filter by default. r250697: Add dependencies on the firmware, which allows the loading of the cxgb and cxgbe modules. Added: stable/9/sys/modules/cxgbe/t4_firmware/ - copied from r248925, head/sys/modules/cxgbe/t4_firmware/ stable/9/tools/tools/cxgbetool/reg_defs_t5.c - copied unchanged from r248925, head/tools/tools/cxgbetool/reg_defs_t5.c Deleted: stable/9/sys/modules/cxgbe/firmware/ Modified: stable/9/share/man/man4/cxgbe.4 stable/9/sys/dev/cxgb/cxgb_main.c stable/9/sys/dev/cxgbe/adapter.h stable/9/sys/dev/cxgbe/common/common.h stable/9/sys/dev/cxgbe/common/t4_hw.c stable/9/sys/dev/cxgbe/common/t4_hw.h stable/9/sys/dev/cxgbe/common/t4_msg.h stable/9/sys/dev/cxgbe/common/t4_regs.h stable/9/sys/dev/cxgbe/firmware/t4fw_interface.h stable/9/sys/dev/cxgbe/offload.h stable/9/sys/dev/cxgbe/osdep.h stable/9/sys/dev/cxgbe/t4_ioctl.h stable/9/sys/dev/cxgbe/t4_main.c stable/9/sys/dev/cxgbe/t4_sge.c stable/9/sys/dev/cxgbe/tom/t4_connect.c stable/9/sys/dev/cxgbe/tom/t4_cpl_io.c stable/9/sys/dev/cxgbe/tom/t4_ddp.c stable/9/sys/dev/cxgbe/tom/t4_listen.c stable/9/sys/dev/cxgbe/tom/t4_tom.c stable/9/sys/dev/cxgbe/tom/t4_tom.h stable/9/sys/modules/cxgbe/Makefile stable/9/tools/tools/cxgbetool/cxgbetool.c Directory Properties: stable/9/share/man/man4/ (props changed) stable/9/sys/ (props changed) stable/9/sys/dev/ (props changed) stable/9/sys/modules/ (props changed) stable/9/tools/tools/cxgbetool/ (props changed) Modified: stable/9/share/man/man4/cxgbe.4 ============================================================================== --- stable/9/share/man/man4/cxgbe.4 Mon Jul 1 23:53:22 2013 (r252494) +++ stable/9/share/man/man4/cxgbe.4 Tue Jul 2 04:27:16 2013 (r252495) @@ -46,9 +46,10 @@ kernel configuration file: .Ed .Pp To load the driver as a -module at boot time, place the following line in +module at boot time, place the following lines in .Xr loader.conf 5 : .Bd -literal -offset indent +t4fw_cfg_load="YES" if_cxgbe_load="YES" .Ed .Sh DESCRIPTION Modified: stable/9/sys/dev/cxgb/cxgb_main.c ============================================================================== --- stable/9/sys/dev/cxgb/cxgb_main.c Mon Jul 1 23:53:22 2013 (r252494) +++ stable/9/sys/dev/cxgb/cxgb_main.c Tue Jul 2 04:27:16 2013 (r252495) @@ -149,6 +149,7 @@ static devclass_t cxgb_controller_devcla DRIVER_MODULE(cxgbc, pci, cxgb_controller_driver, cxgb_controller_devclass, cxgbc_mod_event, 0); MODULE_VERSION(cxgbc, 1); +MODULE_DEPEND(cxgbc, firmware, 1, 1, 1); /* * Attachment glue for the ports. Attachment is done directly to the Modified: stable/9/sys/dev/cxgbe/adapter.h ============================================================================== --- stable/9/sys/dev/cxgbe/adapter.h Mon Jul 1 23:53:22 2013 (r252494) +++ stable/9/sys/dev/cxgbe/adapter.h Tue Jul 2 04:27:16 2013 (r252495) @@ -50,9 +50,6 @@ #include "offload.h" #include "firmware/t4fw_interface.h" -#define T4_CFGNAME "t4fw_cfg" -#define T4_FWNAME "t4fw" - MALLOC_DECLARE(M_CXGBE); #define CXGBE_UNIMPLEMENTED(s) \ panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) @@ -144,12 +141,6 @@ enum { TX_WR_FLITS = SGE_MAX_WR_LEN / 8 }; -#ifdef T4_PKT_TIMESTAMP -#define RX_COPY_THRESHOLD (MINCLSIZE - 8) -#else -#define RX_COPY_THRESHOLD MINCLSIZE -#endif - enum { /* adapter intr_type */ INTR_INTX = (1 << 0), @@ -327,6 +318,9 @@ enum { EQ_STALLED = (1 << 6), /* out of hw descriptors or dmamaps */ }; +/* Listed in order of preference. Update t4_sysctls too if you change these */ +enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; + /* * Egress Queue: driver is producer, T4 is consumer. * @@ -344,6 +338,9 @@ struct sge_eq { struct tx_desc *desc; /* KVA of descriptor ring */ bus_addr_t ba; /* bus address of descriptor ring */ struct sge_qstat *spg; /* status page, for convenience */ + int doorbells; + volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ + u_int udb_qid; /* relative qid within the doorbell page */ uint16_t cap; /* max # of desc, for convenience */ uint16_t avail; /* available descriptors, for convenience */ uint16_t qsize; /* size (# of entries) of the queue */ @@ -496,6 +493,7 @@ struct sge { int timer_val[SGE_NTIMERS]; int counter_val[SGE_NCOUNTERS]; int fl_starve_threshold; + int s_qpp; int nrxq; /* total # of Ethernet rx queues */ int ntxq; /* total # of Ethernet tx tx queues */ @@ -541,6 +539,9 @@ struct adapter { bus_space_handle_t bh; bus_space_tag_t bt; bus_size_t mmio_len; + int udbs_rid; + struct resource *udbs_res; + volatile uint8_t *udbs_base; unsigned int pf; unsigned int mbox; @@ -570,6 +571,7 @@ struct adapter { struct l2t_data *l2t; /* L2 table */ struct tid_info tids; + int doorbells; int open_device_map; #ifdef TCP_OFFLOAD int offload_map; @@ -748,13 +750,22 @@ t4_os_set_hw_addr(struct adapter *sc, in bcopy(hw_addr, sc->port[idx]->hw_addr, ETHER_ADDR_LEN); } -static inline bool is_10G_port(const struct port_info *pi) +static inline bool +is_10G_port(const struct port_info *pi) { return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0); } -static inline int tx_resume_threshold(struct sge_eq *eq) +static inline bool +is_40G_port(const struct port_info *pi) +{ + + return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) != 0); +} + +static inline int +tx_resume_threshold(struct sge_eq *eq) { return (eq->qsize / 4); @@ -778,7 +789,9 @@ void end_synchronized_op(struct adapter /* t4_sge.c */ void t4_sge_modload(void); -int t4_sge_init(struct adapter *); +void t4_init_sge_cpl_handlers(struct adapter *); +void t4_tweak_chip_settings(struct adapter *); +int t4_read_chip_settings(struct adapter *); int t4_create_dma_tag(struct adapter *); int t4_destroy_dma_tag(struct adapter *); int t4_setup_adapter_queues(struct adapter *); Modified: stable/9/sys/dev/cxgbe/common/common.h ============================================================================== --- stable/9/sys/dev/cxgbe/common/common.h Mon Jul 1 23:53:22 2013 (r252494) +++ stable/9/sys/dev/cxgbe/common/common.h Tue Jul 2 04:27:16 2013 (r252495) @@ -42,15 +42,19 @@ enum { MACADDR_LEN = 12, /* MAC Address length */ }; -enum { MEM_EDC0, MEM_EDC1, MEM_MC }; +enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 }; enum { MEMWIN0_APERTURE = 2048, MEMWIN0_BASE = 0x1b800, MEMWIN1_APERTURE = 32768, MEMWIN1_BASE = 0x28000, - MEMWIN2_APERTURE = 65536, - MEMWIN2_BASE = 0x30000, + + MEMWIN2_APERTURE_T4 = 65536, + MEMWIN2_BASE_T4 = 0x30000, + + MEMWIN2_APERTURE_T5 = 128 * 1024, + MEMWIN2_BASE_T5 = 0x60000, }; enum dev_master { MASTER_CANT, MASTER_MAY, MASTER_MUST }; @@ -63,15 +67,20 @@ enum { PAUSE_AUTONEG = 1 << 2 }; -#define FW_VERSION_MAJOR 1 -#define FW_VERSION_MINOR 8 -#define FW_VERSION_MICRO 4 -#define FW_VERSION_BUILD 0 - -#define FW_VERSION (V_FW_HDR_FW_VER_MAJOR(FW_VERSION_MAJOR) | \ - V_FW_HDR_FW_VER_MINOR(FW_VERSION_MINOR) | \ - V_FW_HDR_FW_VER_MICRO(FW_VERSION_MICRO) | \ - V_FW_HDR_FW_VER_BUILD(FW_VERSION_BUILD)) +#define FW_VERSION_MAJOR_T4 1 +#define FW_VERSION_MINOR_T4 8 +#define FW_VERSION_MICRO_T4 4 +#define FW_VERSION_BUILD_T4 0 + +#define FW_VERSION_MAJOR_T5 0 +#define FW_VERSION_MINOR_T5 5 +#define FW_VERSION_MICRO_T5 18 +#define FW_VERSION_BUILD_T5 0 + +struct memwin { + uint32_t base; + uint32_t aperture; +}; struct port_stats { u64 tx_octets; /* total # of octets in good frames */ @@ -267,18 +276,20 @@ struct adapter_params { unsigned int cim_la_size; - /* Used as int in sysctls, do not reduce size */ - unsigned int nports; /* # of ethernet ports */ - unsigned int portvec; - unsigned int rev; /* chip revision */ - unsigned int offload; + uint8_t nports; /* # of ethernet ports */ + uint8_t portvec; + unsigned int chipid:4; /* chip ID. T4 = 4, T5 = 5, ... */ + unsigned int rev:4; /* chip revision */ + unsigned int fpga:1; /* this is an FPGA */ + unsigned int offload:1; /* hw is TOE capable, fw has divvied up card + resources for TOE operation. */ + unsigned int bypass:1; /* this is a bypass card */ unsigned int ofldq_wr_cred; }; -enum { /* chip revisions */ - T4_REV_A = 0, -}; +#define CHELSIO_T4 0x4 +#define CHELSIO_T5 0x5 struct trace_params { u32 data[TRACE_LEN / 4]; @@ -316,6 +327,31 @@ static inline int is_offload(const struc return adap->params.offload; } +static inline int chip_id(struct adapter *adap) +{ + return adap->params.chipid; +} + +static inline int chip_rev(struct adapter *adap) +{ + return adap->params.rev; +} + +static inline int is_t4(struct adapter *adap) +{ + return adap->params.chipid == CHELSIO_T4; +} + +static inline int is_t5(struct adapter *adap) +{ + return adap->params.chipid == CHELSIO_T5; +} + +static inline int is_fpga(struct adapter *adap) +{ + return adap->params.fpga; +} + static inline unsigned int core_ticks_per_usec(const struct adapter *adap) { return adap->params.vpd.cclk / 1000; @@ -388,7 +424,7 @@ int t4_read_flash(struct adapter *adapte int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); int t4_load_boot(struct adapter *adap, u8 *boot_data, unsigned int boot_addr, unsigned int size); -unsigned int t4_flash_cfg_addr(struct adapter *adapter); +int t4_flash_cfg_addr(struct adapter *adapter); int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); int t4_get_fw_version(struct adapter *adapter, u32 *vers); int t4_get_tp_version(struct adapter *adapter, u32 *vers); @@ -437,7 +473,8 @@ int t4_cim_read_la(struct adapter *adap, void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, unsigned int *pif_req_wrptr, unsigned int *pif_rsp_wrptr); void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); -int t4_mc_read(struct adapter *adap, u32 addr, __be32 *data, u64 *parity); +int t4_mc_read(struct adapter *adap, int idx, u32 addr, + __be32 *data, u64 *parity); int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *parity); int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 size, __be32 *data); Modified: stable/9/sys/dev/cxgbe/common/t4_hw.c ============================================================================== --- stable/9/sys/dev/cxgbe/common/t4_hw.c Mon Jul 1 23:53:22 2013 (r252494) +++ stable/9/sys/dev/cxgbe/common/t4_hw.c Tue Jul 2 04:27:16 2013 (r252495) @@ -176,9 +176,7 @@ static void t4_report_fw_error(struct ad u32 pcie_fw; pcie_fw = t4_read_reg(adap, A_PCIE_FW); - if (!(pcie_fw & F_PCIE_FW_ERR)) - CH_ERR(adap, "Firmware error report called with no error\n"); - else + if (pcie_fw & F_PCIE_FW_ERR) CH_ERR(adap, "Firmware reports adapter error: %s\n", reason[G_PCIE_FW_EVAL(pcie_fw)]); } @@ -312,6 +310,7 @@ int t4_wr_mbox_meat(struct adapter *adap /** * t4_mc_read - read from MC through backdoor accesses * @adap: the adapter + * @idx: which MC to access * @addr: address of first byte requested * @data: 64 bytes of data containing the requested address * @ecc: where to store the corresponding 64-bit ECC word @@ -320,22 +319,40 @@ int t4_wr_mbox_meat(struct adapter *adap * that covers the requested address @addr. If @parity is not %NULL it * is assigned the 64-bit ECC word for the read data. */ -int t4_mc_read(struct adapter *adap, u32 addr, __be32 *data, u64 *ecc) +int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc) { int i; + u32 mc_bist_cmd_reg, mc_bist_cmd_addr_reg, mc_bist_cmd_len_reg; + u32 mc_bist_status_rdata_reg, mc_bist_data_pattern_reg; + + if (is_t4(adap)) { + mc_bist_cmd_reg = A_MC_BIST_CMD; + mc_bist_cmd_addr_reg = A_MC_BIST_CMD_ADDR; + mc_bist_cmd_len_reg = A_MC_BIST_CMD_LEN; + mc_bist_status_rdata_reg = A_MC_BIST_STATUS_RDATA; + mc_bist_data_pattern_reg = A_MC_BIST_DATA_PATTERN; + } else { + mc_bist_cmd_reg = MC_REG(A_MC_P_BIST_CMD, idx); + mc_bist_cmd_addr_reg = MC_REG(A_MC_P_BIST_CMD_ADDR, idx); + mc_bist_cmd_len_reg = MC_REG(A_MC_P_BIST_CMD_LEN, idx); + mc_bist_status_rdata_reg = MC_REG(A_MC_P_BIST_STATUS_RDATA, + idx); + mc_bist_data_pattern_reg = MC_REG(A_MC_P_BIST_DATA_PATTERN, + idx); + } - if (t4_read_reg(adap, A_MC_BIST_CMD) & F_START_BIST) + if (t4_read_reg(adap, mc_bist_cmd_reg) & F_START_BIST) return -EBUSY; - t4_write_reg(adap, A_MC_BIST_CMD_ADDR, addr & ~0x3fU); - t4_write_reg(adap, A_MC_BIST_CMD_LEN, 64); - t4_write_reg(adap, A_MC_BIST_DATA_PATTERN, 0xc); - t4_write_reg(adap, A_MC_BIST_CMD, V_BIST_OPCODE(1) | F_START_BIST | - V_BIST_CMD_GAP(1)); - i = t4_wait_op_done(adap, A_MC_BIST_CMD, F_START_BIST, 0, 10, 1); + t4_write_reg(adap, mc_bist_cmd_addr_reg, addr & ~0x3fU); + t4_write_reg(adap, mc_bist_cmd_len_reg, 64); + t4_write_reg(adap, mc_bist_data_pattern_reg, 0xc); + t4_write_reg(adap, mc_bist_cmd_reg, V_BIST_OPCODE(1) | + F_START_BIST | V_BIST_CMD_GAP(1)); + i = t4_wait_op_done(adap, mc_bist_cmd_reg, F_START_BIST, 0, 10, 1); if (i) return i; -#define MC_DATA(i) MC_BIST_STATUS_REG(A_MC_BIST_STATUS_RDATA, i) +#define MC_DATA(i) MC_BIST_STATUS_REG(mc_bist_status_rdata_reg, i) for (i = 15; i >= 0; i--) *data++ = ntohl(t4_read_reg(adap, MC_DATA(i))); @@ -360,20 +377,47 @@ int t4_mc_read(struct adapter *adap, u32 int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc) { int i; + u32 edc_bist_cmd_reg, edc_bist_cmd_addr_reg, edc_bist_cmd_len_reg; + u32 edc_bist_cmd_data_pattern, edc_bist_status_rdata_reg; - idx *= EDC_STRIDE; - if (t4_read_reg(adap, A_EDC_BIST_CMD + idx) & F_START_BIST) + if (is_t4(adap)) { + edc_bist_cmd_reg = EDC_REG(A_EDC_BIST_CMD, idx); + edc_bist_cmd_addr_reg = EDC_REG(A_EDC_BIST_CMD_ADDR, idx); + edc_bist_cmd_len_reg = EDC_REG(A_EDC_BIST_CMD_LEN, idx); + edc_bist_cmd_data_pattern = EDC_REG(A_EDC_BIST_DATA_PATTERN, + idx); + edc_bist_status_rdata_reg = EDC_REG(A_EDC_BIST_STATUS_RDATA, + idx); + } else { +/* + * These macro are missing in t4_regs.h file. + * Added temporarily for testing. + */ +#define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR) +#define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx) + edc_bist_cmd_reg = EDC_REG_T5(A_EDC_H_BIST_CMD, idx); + edc_bist_cmd_addr_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_ADDR, idx); + edc_bist_cmd_len_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_LEN, idx); + edc_bist_cmd_data_pattern = EDC_REG_T5(A_EDC_H_BIST_DATA_PATTERN, + idx); + edc_bist_status_rdata_reg = EDC_REG_T5(A_EDC_H_BIST_STATUS_RDATA, + idx); +#undef EDC_REG_T5 +#undef EDC_STRIDE_T5 + } + + if (t4_read_reg(adap, edc_bist_cmd_reg) & F_START_BIST) return -EBUSY; - t4_write_reg(adap, A_EDC_BIST_CMD_ADDR + idx, addr & ~0x3fU); - t4_write_reg(adap, A_EDC_BIST_CMD_LEN + idx, 64); - t4_write_reg(adap, A_EDC_BIST_DATA_PATTERN + idx, 0xc); - t4_write_reg(adap, A_EDC_BIST_CMD + idx, + t4_write_reg(adap, edc_bist_cmd_addr_reg, addr & ~0x3fU); + t4_write_reg(adap, edc_bist_cmd_len_reg, 64); + t4_write_reg(adap, edc_bist_cmd_data_pattern, 0xc); + t4_write_reg(adap, edc_bist_cmd_reg, V_BIST_OPCODE(1) | V_BIST_CMD_GAP(1) | F_START_BIST); - i = t4_wait_op_done(adap, A_EDC_BIST_CMD + idx, F_START_BIST, 0, 10, 1); + i = t4_wait_op_done(adap, edc_bist_cmd_reg, F_START_BIST, 0, 10, 1); if (i) return i; -#define EDC_DATA(i) (EDC_BIST_STATUS_REG(A_EDC_BIST_STATUS_RDATA, i) + idx) +#define EDC_DATA(i) EDC_BIST_STATUS_REG(edc_bist_status_rdata_reg, i) for (i = 15; i >= 0; i--) *data++ = ntohl(t4_read_reg(adap, EDC_DATA(i))); @@ -425,8 +469,8 @@ int t4_mem_read(struct adapter *adap, in /* * Read the chip's memory block and bail if there's an error. */ - if (mtype == MEM_MC) - ret = t4_mc_read(adap, pos, data, NULL); + if ((mtype == MEM_MC) || (mtype == MEM_MC1)) + ret = t4_mc_read(adap, mtype - MEM_MC, pos, data, NULL); else ret = t4_edc_read(adap, mtype, pos, data, NULL); if (ret) @@ -464,8 +508,9 @@ struct t4_vpd_hdr { #define EEPROM_STAT_ADDR 0x7bfc #define VPD_BASE 0x400 #define VPD_BASE_OLD 0 -#define VPD_LEN 512 +#define VPD_LEN 1024 #define VPD_INFO_FLD_HDR_SIZE 3 +#define CHELSIO_VPD_UNIQUE_ID 0x82 /** * t4_seeprom_read - read a serial EEPROM location @@ -630,7 +675,7 @@ static int get_vpd_params(struct adapter * it at 0. */ ret = t4_seeprom_read(adapter, VPD_BASE, (u32 *)(vpd)); - addr = *vpd == 0x82 ? VPD_BASE : VPD_BASE_OLD; + addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD; for (i = 0; i < sizeof(vpd); i += 4) { ret = t4_seeprom_read(adapter, addr + i, (u32 *)(vpd + i)); @@ -668,8 +713,10 @@ static int get_vpd_params(struct adapter i = vpd[sn - VPD_INFO_FLD_HDR_SIZE + 2]; memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN)); strstrip(p->sn); + i = vpd[pn - VPD_INFO_FLD_HDR_SIZE + 2]; memcpy(p->pn, vpd + pn, min(i, PN_LEN)); strstrip((char *)p->pn); + i = vpd[na - VPD_INFO_FLD_HDR_SIZE + 2]; memcpy(p->na, vpd + na, min(i, MACADDR_LEN)); strstrip((char *)p->na); @@ -914,6 +961,7 @@ int t4_get_tp_version(struct adapter *ad int t4_check_fw_version(struct adapter *adapter) { int ret, major, minor, micro; + int exp_major, exp_minor, exp_micro; ret = t4_get_fw_version(adapter, &adapter->params.fw_vers); if (!ret) @@ -925,13 +973,30 @@ int t4_check_fw_version(struct adapter * minor = G_FW_HDR_FW_VER_MINOR(adapter->params.fw_vers); micro = G_FW_HDR_FW_VER_MICRO(adapter->params.fw_vers); - if (major != FW_VERSION_MAJOR) { /* major mismatch - fail */ + switch (chip_id(adapter)) { + case CHELSIO_T4: + exp_major = FW_VERSION_MAJOR_T4; + exp_minor = FW_VERSION_MINOR_T4; + exp_micro = FW_VERSION_MICRO_T4; + break; + case CHELSIO_T5: + exp_major = FW_VERSION_MAJOR_T5; + exp_minor = FW_VERSION_MINOR_T5; + exp_micro = FW_VERSION_MICRO_T5; + break; + default: + CH_ERR(adapter, "Unsupported chip type, %x\n", + chip_id(adapter)); + return -EINVAL; + } + + if (major != exp_major) { /* major mismatch - fail */ CH_ERR(adapter, "card FW has major version %u, driver wants " - "%u\n", major, FW_VERSION_MAJOR); + "%u\n", major, exp_major); return -EINVAL; } - if (minor == FW_VERSION_MINOR && micro == FW_VERSION_MICRO) + if (minor == exp_minor && micro == exp_micro) return 0; /* perfect match */ /* Minor/micro version mismatch. Report it but often it's OK. */ @@ -970,14 +1035,19 @@ static int t4_flash_erase_sectors(struct * @adapter: the adapter * * Return the address within the flash where the Firmware Configuration - * File is stored. + * File is stored, or an error if the device FLASH is too small to contain + * a Firmware Configuration File. */ -unsigned int t4_flash_cfg_addr(struct adapter *adapter) +int t4_flash_cfg_addr(struct adapter *adapter) { - if (adapter->params.sf_size == 0x100000) - return FLASH_FPGA_CFG_START; - else - return FLASH_CFG_START; + /* + * If the device FLASH isn't large enough to hold a Firmware + * Configuration File, return an error. + */ + if (adapter->params.sf_size < FLASH_CFG_START + FLASH_CFG_MAX_SIZE) + return -ENOSPC; + + return FLASH_CFG_START; } /** @@ -990,12 +1060,16 @@ unsigned int t4_flash_cfg_addr(struct ad */ int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size) { - int ret, i, n; + int ret, i, n, cfg_addr; unsigned int addr; unsigned int flash_cfg_start_sec; unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; - addr = t4_flash_cfg_addr(adap); + cfg_addr = t4_flash_cfg_addr(adap); + if (cfg_addr < 0) + return cfg_addr; + + addr = cfg_addr; flash_cfg_start_sec = addr / SF_SEC_SIZE; if (size > FLASH_CFG_MAX_SIZE) { @@ -1072,6 +1146,13 @@ int t4_load_fw(struct adapter *adap, con FLASH_FW_MAX_SIZE); return -EFBIG; } + if ((is_t4(adap) && hdr->chip != FW_HDR_CHIP_T4) || + (is_t5(adap) && hdr->chip != FW_HDR_CHIP_T5)) { + CH_ERR(adap, + "FW image (%d) is not suitable for this adapter (%d)\n", + hdr->chip, chip_id(adap)); + return -EINVAL; + } for (csum = 0, i = 0; i < size / sizeof(csum); i++) csum += ntohl(p[i]); @@ -1407,6 +1488,7 @@ out: void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres) { unsigned int i, v; + int cim_num_obq = is_t4(adap) ? CIM_NUM_OBQ : CIM_NUM_OBQ_T5; for (i = 0; i < CIM_NUM_IBQ; i++) { t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_IBQSELECT | @@ -1416,7 +1498,7 @@ void t4_read_cimq_cfg(struct adapter *ad *size++ = G_CIMQSIZE(v) * 256; /* value is in 256-byte units */ *thres++ = G_QUEFULLTHRSH(v) * 8; /* 8-byte unit */ } - for (i = 0; i < CIM_NUM_OBQ; i++) { + for (i = 0; i < cim_num_obq; i++) { t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT | V_QUENUMSELECT(i)); v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL); @@ -1452,8 +1534,12 @@ int t4_read_cim_ibq(struct adapter *adap for (i = 0; i < n; i++, addr++) { t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, V_IBQDBGADDR(addr) | F_IBQDBGEN); + /* + * It might take 3-10ms before the IBQ debug read access is + * allowed. Wait for 1 Sec with a delay of 1 usec. + */ err = t4_wait_op_done(adap, A_CIM_IBQ_DBG_CFG, F_IBQDBGBUSY, 0, - 2, 1); + 1000000, 1); if (err) return err; *data++ = t4_read_reg(adap, A_CIM_IBQ_DBG_DATA); @@ -1477,8 +1563,9 @@ int t4_read_cim_obq(struct adapter *adap { int i, err; unsigned int addr, v, nwords; + int cim_num_obq = is_t4(adap) ? CIM_NUM_OBQ : CIM_NUM_OBQ_T5; - if (qid > 5 || (n & 3)) + if (qid >= cim_num_obq || (n & 3)) return -EINVAL; t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT | @@ -1762,7 +1849,8 @@ void t4_ulprx_read_la(struct adapter *ad } #define ADVERT_MASK (FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G |\ - FW_PORT_CAP_SPEED_10G | FW_PORT_CAP_ANEG) + FW_PORT_CAP_SPEED_10G | FW_PORT_CAP_SPEED_40G | \ + FW_PORT_CAP_SPEED_100G | FW_PORT_CAP_ANEG) /** * t4_link_start - apply link configuration to MAC/PHY @@ -1933,6 +2021,47 @@ static void pcie_intr_handler(struct ada { 0 } }; + static struct intr_info t5_pcie_intr_info[] = { + { F_MSTGRPPERR, "Master Response Read Queue parity error", + -1, 1 }, + { F_MSTTIMEOUTPERR, "Master Timeout FIFO parity error", -1, 1 }, + { F_MSIXSTIPERR, "MSI-X STI SRAM parity error", -1, 1 }, + { F_MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 }, + { F_MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 }, + { F_MSIXDATAPERR, "MSI-X data parity error", -1, 1 }, + { F_MSIXDIPERR, "MSI-X DI parity error", -1, 1 }, + { F_PIOCPLGRPPERR, "PCI PIO completion Group FIFO parity error", + -1, 1 }, + { F_PIOREQGRPPERR, "PCI PIO request Group FIFO parity error", + -1, 1 }, + { F_TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 }, + { F_MSTTAGQPERR, "PCI master tag queue parity error", -1, 1 }, + { F_CREQPERR, "PCI CMD channel request parity error", -1, 1 }, + { F_CRSPPERR, "PCI CMD channel response parity error", -1, 1 }, + { F_DREQWRPERR, "PCI DMA channel write request parity error", + -1, 1 }, + { F_DREQPERR, "PCI DMA channel request parity error", -1, 1 }, + { F_DRSPPERR, "PCI DMA channel response parity error", -1, 1 }, + { F_HREQWRPERR, "PCI HMA channel count parity error", -1, 1 }, + { F_HREQPERR, "PCI HMA channel request parity error", -1, 1 }, + { F_HRSPPERR, "PCI HMA channel response parity error", -1, 1 }, + { F_CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 }, + { F_FIDPERR, "PCI FID parity error", -1, 1 }, + { F_VFIDPERR, "PCI INTx clear parity error", -1, 1 }, + { F_MAGRPPERR, "PCI MA group FIFO parity error", -1, 1 }, + { F_PIOTAGPERR, "PCI PIO tag parity error", -1, 1 }, + { F_IPRXHDRGRPPERR, "PCI IP Rx header group parity error", + -1, 1 }, + { F_IPRXDATAGRPPERR, "PCI IP Rx data group parity error", + -1, 1 }, + { F_RPLPERR, "PCI IP replay buffer parity error", -1, 1 }, + { F_IPSOTPERR, "PCI IP SOT buffer parity error", -1, 1 }, + { F_TRGT1GRPPERR, "PCI TRGT1 group FIFOs parity error", -1, 1 }, + { F_READRSPERR, "Outbound read error", -1, + 0 }, + { 0 } + }; + int fat; fat = t4_handle_intr_status(adapter, @@ -1941,7 +2070,9 @@ static void pcie_intr_handler(struct ada t4_handle_intr_status(adapter, A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS, pcie_port_intr_info) + - t4_handle_intr_status(adapter, A_PCIE_INT_CAUSE, pcie_intr_info); + t4_handle_intr_status(adapter, A_PCIE_INT_CAUSE, + is_t4(adapter) ? + pcie_intr_info : t5_pcie_intr_info); if (fat) t4_fatal_err(adapter); } @@ -2286,8 +2417,13 @@ static void mem_intr_handler(struct adap addr = EDC_REG(A_EDC_INT_CAUSE, idx); cnt_addr = EDC_REG(A_EDC_ECC_STATUS, idx); } else { - addr = A_MC_INT_CAUSE; - cnt_addr = A_MC_ECC_STATUS; + if (is_t4(adapter)) { + addr = A_MC_INT_CAUSE; + cnt_addr = A_MC_ECC_STATUS; + } else { + addr = A_MC_P_INT_CAUSE; + cnt_addr = A_MC_P_ECC_STATUS; + } } v = t4_read_reg(adapter, addr) & MEM_INT_MASK; @@ -2368,9 +2504,15 @@ static void ncsi_intr_handler(struct ada */ static void xgmac_intr_handler(struct adapter *adap, int port) { - u32 v = t4_read_reg(adap, PORT_REG(port, A_XGMAC_PORT_INT_CAUSE)); + u32 v, int_cause_reg; + + if (is_t4(adap)) + int_cause_reg = PORT_REG(port, A_XGMAC_PORT_INT_CAUSE); + else + int_cause_reg = T5_PORT_REG(port, A_MAC_PORT_INT_CAUSE); - v &= F_TXFIFO_PRTY_ERR | F_RXFIFO_PRTY_ERR; + v = t4_read_reg(adap, int_cause_reg); + v &= (F_TXFIFO_PRTY_ERR | F_RXFIFO_PRTY_ERR); if (!v) return; @@ -2378,7 +2520,7 @@ static void xgmac_intr_handler(struct ad CH_ALERT(adap, "XGMAC %d Tx FIFO parity error\n", port); if (v & F_RXFIFO_PRTY_ERR) CH_ALERT(adap, "XGMAC %d Rx FIFO parity error\n", port); - t4_write_reg(adap, PORT_REG(port, A_XGMAC_PORT_INT_CAUSE), v); + t4_write_reg(adap, int_cause_reg, v); t4_fatal_err(adap); } @@ -2388,12 +2530,19 @@ static void xgmac_intr_handler(struct ad static void pl_intr_handler(struct adapter *adap) { static struct intr_info pl_intr_info[] = { - { F_FATALPERR, "T4 fatal parity error", -1, 1 }, + { F_FATALPERR, "Fatal parity error", -1, 1 }, { F_PERRVFID, "PL VFID_MAP parity error", -1, 1 }, { 0 } }; - if (t4_handle_intr_status(adap, A_PL_PL_INT_CAUSE, pl_intr_info)) + static struct intr_info t5_pl_intr_info[] = { + { F_PL_BUSPERR, "PL bus parity error", -1, 1 }, + { F_FATALPERR, "Fatal parity error", -1, 1 }, + { 0 } + }; + + if (t4_handle_intr_status(adap, A_PL_PL_INT_CAUSE, + is_t4(adap) ? pl_intr_info : t5_pl_intr_info)) t4_fatal_err(adap); } @@ -2526,7 +2675,6 @@ void t4_intr_clear(struct adapter *adapt A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS, A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS, A_PCIE_NONFAT_ERR, A_PCIE_INT_CAUSE, - A_MC_INT_CAUSE, A_MA_INT_WRAP_STATUS, A_MA_PARITY_ERROR_STATUS, A_MA_INT_CAUSE, A_EDC_INT_CAUSE, EDC_REG(A_EDC_INT_CAUSE, 1), A_CIM_HOST_INT_CAUSE, A_CIM_HOST_UPACC_INT_CAUSE, @@ -2546,6 +2694,9 @@ void t4_intr_clear(struct adapter *adapt for (i = 0; i < ARRAY_SIZE(cause_reg); ++i) t4_write_reg(adapter, cause_reg[i], 0xffffffff); + t4_write_reg(adapter, is_t4(adapter) ? A_MC_INT_CAUSE : + A_MC_P_INT_CAUSE, 0xffffffff); + t4_write_reg(adapter, A_PL_INT_CAUSE, GLBL_INTR_MASK); (void) t4_read_reg(adapter, A_PL_INT_CAUSE); /* flush */ } @@ -3531,7 +3682,10 @@ int t4_set_trace_filter(struct adapter * V_TFMINPKTSIZE(tp->min_len)); t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, V_TFOFFSET(tp->skip_ofst) | V_TFLENGTH(tp->skip_len) | - V_TFPORT(tp->port) | F_TFEN | V_TFINVERTMATCH(tp->invert)); + is_t4(adap) ? + V_TFPORT(tp->port) | F_TFEN | V_TFINVERTMATCH(tp->invert) : + V_T5_TFPORT(tp->port) | F_T5_TFEN | + V_T5_TFINVERTMATCH(tp->invert)); return 0; } @@ -3555,13 +3709,18 @@ void t4_get_trace_filter(struct adapter ctla = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst); ctlb = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst); - *enabled = !!(ctla & F_TFEN); + if (is_t4(adap)) { + *enabled = !!(ctla & F_TFEN); + tp->port = G_TFPORT(ctla); + } else { + *enabled = !!(ctla & F_T5_TFEN); + tp->port = G_T5_TFPORT(ctla); + } tp->snap_len = G_TFCAPTUREMAX(ctlb); tp->min_len = G_TFMINPKTSIZE(ctlb); tp->skip_ofst = G_TFOFFSET(ctla); tp->skip_len = G_TFLENGTH(ctla); tp->invert = !!(ctla & F_TFINVERTMATCH); - tp->port = G_TFPORT(ctla); ofst = (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH) * idx; data_reg = A_MPS_TRC_FILTER0_MATCH + ofst; @@ -3584,11 +3743,19 @@ void t4_get_trace_filter(struct adapter void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]) { int i; + u32 data[2]; for (i = 0; i < PM_NSTATS; i++) { t4_write_reg(adap, A_PM_TX_STAT_CONFIG, i + 1); cnt[i] = t4_read_reg(adap, A_PM_TX_STAT_COUNT); - cycles[i] = t4_read_reg64(adap, A_PM_TX_STAT_LSB); + if (is_t4(adap)) + cycles[i] = t4_read_reg64(adap, A_PM_TX_STAT_LSB); + else { + t4_read_indirect(adap, A_PM_TX_DBG_CTRL, + A_PM_TX_DBG_DATA, data, 2, + A_PM_TX_DBG_STAT_MSB); + cycles[i] = (((u64)data[0] << 32) | data[1]); + } } } @@ -3603,11 +3770,19 @@ void t4_pmtx_get_stats(struct adapter *a void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]) { int i; + u32 data[2]; for (i = 0; i < PM_NSTATS; i++) { t4_write_reg(adap, A_PM_RX_STAT_CONFIG, i + 1); cnt[i] = t4_read_reg(adap, A_PM_RX_STAT_COUNT); - cycles[i] = t4_read_reg64(adap, A_PM_RX_STAT_LSB); + if (is_t4(adap)) + cycles[i] = t4_read_reg64(adap, A_PM_RX_STAT_LSB); + else { + t4_read_indirect(adap, A_PM_RX_DBG_CTRL, + A_PM_RX_DBG_DATA, data, 2, + A_PM_RX_DBG_STAT_MSB); + cycles[i] = (((u64)data[0] << 32) | data[1]); + } } } @@ -3666,7 +3841,9 @@ void t4_get_port_stats(struct adapter *a u32 bgmap = get_mps_bg_map(adap, idx); #define GET_STAT(name) \ - t4_read_reg64(adap, PORT_REG(idx, A_MPS_PORT_STAT_##name##_L)) + t4_read_reg64(adap, \ + (is_t4(adap) ? PORT_REG(idx, A_MPS_PORT_STAT_##name##_L) : \ + T5_PORT_REG(idx, A_MPS_PORT_STAT_##name##_L))) #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L) p->tx_pause = GET_STAT(TX_PORT_PAUSE); @@ -3745,13 +3922,19 @@ void t4_clr_port_stats(struct adapter *a { unsigned int i; u32 bgmap = get_mps_bg_map(adap, idx); + u32 port_base_addr; + + if (is_t4(adap)) + port_base_addr = PORT_BASE(idx); + else + port_base_addr = T5_PORT_BASE(idx); for (i = A_MPS_PORT_STAT_TX_PORT_BYTES_L; - i <= A_MPS_PORT_STAT_TX_PORT_PPP7_H; i += 8) - t4_write_reg(adap, PORT_REG(idx, i), 0); + i <= A_MPS_PORT_STAT_TX_PORT_PPP7_H; i += 8) + t4_write_reg(adap, port_base_addr + i, 0); for (i = A_MPS_PORT_STAT_RX_PORT_BYTES_L; - i <= A_MPS_PORT_STAT_RX_PORT_LESS_64B_H; i += 8) - t4_write_reg(adap, PORT_REG(idx, i), 0); + i <= A_MPS_PORT_STAT_RX_PORT_LESS_64B_H; i += 8) + t4_write_reg(adap, port_base_addr + i, 0); for (i = 0; i < 4; i++) if (bgmap & (1 << i)) { t4_write_reg(adap, @@ -3774,7 +3957,10 @@ void t4_get_lb_stats(struct adapter *ada u32 bgmap = get_mps_bg_map(adap, idx); #define GET_STAT(name) \ - t4_read_reg64(adap, PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L)) + t4_read_reg64(adap, \ + (is_t4(adap) ? \ + PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L) : \ + T5_PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L))) #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L) p->octets = GET_STAT(BYTES); @@ -3791,8 +3977,7 @@ void t4_get_lb_stats(struct adapter *ada p->frames_512_1023 = GET_STAT(512B_1023B); p->frames_1024_1518 = GET_STAT(1024B_1518B); p->frames_1519_max = GET_STAT(1519B_MAX); - p->drop = t4_read_reg(adap, PORT_REG(idx, - A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES)); + p->drop = GET_STAT(DROP_FRAMES); p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0; p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0; @@ -3818,14 +4003,26 @@ void t4_get_lb_stats(struct adapter *ada void t4_wol_magic_enable(struct adapter *adap, unsigned int port, const u8 *addr) { + u32 mag_id_reg_l, mag_id_reg_h, port_cfg_reg; + + if (is_t4(adap)) { + mag_id_reg_l = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_LO); + mag_id_reg_h = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_HI); + port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2); + } else { + mag_id_reg_l = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_LO); + mag_id_reg_h = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_HI); + port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2); + } + if (addr) { - t4_write_reg(adap, PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_LO), + t4_write_reg(adap, mag_id_reg_l, (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | addr[5]); - t4_write_reg(adap, PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_HI), + t4_write_reg(adap, mag_id_reg_h, (addr[0] << 8) | addr[1]); } - t4_set_reg_field(adap, PORT_REG(port, A_XGMAC_PORT_CFG2), F_MAGICEN, + t4_set_reg_field(adap, port_cfg_reg, F_MAGICEN, V_MAGICEN(addr != NULL)); } @@ -3848,16 +4045,23 @@ int t4_wol_pat_enable(struct adapter *ad u64 mask0, u64 mask1, unsigned int crc, bool enable) { int i; + u32 port_cfg_reg; + + if (is_t4(adap)) + port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2); + else + port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2); if (!enable) { - t4_set_reg_field(adap, PORT_REG(port, A_XGMAC_PORT_CFG2), - F_PATEN, 0); + t4_set_reg_field(adap, port_cfg_reg, F_PATEN, 0); return 0; } if (map > 0xff) return -EINVAL; -#define EPIO_REG(name) PORT_REG(port, A_XGMAC_PORT_EPIO_##name) +#define EPIO_REG(name) \ + (is_t4(adap) ? PORT_REG(port, A_XGMAC_PORT_EPIO_##name) : \ + T5_PORT_REG(port, A_MAC_PORT_EPIO_##name)) t4_write_reg(adap, EPIO_REG(DATA1), mask0 >> 32); t4_write_reg(adap, EPIO_REG(DATA2), mask1); @@ -3883,7 +4087,7 @@ int t4_wol_pat_enable(struct adapter *ad } #undef EPIO_REG - t4_set_reg_field(adap, PORT_REG(port, A_XGMAC_PORT_CFG2), 0, F_PATEN); + t4_set_reg_field(adap, port_cfg_reg, 0, F_PATEN); return 0; } @@ -4487,8 +4691,8 @@ int t4_query_params(struct adapter *adap V_FW_PARAMS_CMD_VFN(vf)); c.retval_len16 = htonl(FW_LEN16(c)); - for (i = 0; i < nparams; i++, p += 2) - *p = htonl(*params++); + for (i = 0; i < nparams; i++, p += 2, params++) + *p = htonl(*params); ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); if (ret == 0) @@ -4527,8 +4731,10 @@ int t4_set_params(struct adapter *adap, c.retval_len16 = htonl(FW_LEN16(c)); while (nparams--) { - *p++ = htonl(*params++); - *p++ = htonl(*val++); + *p++ = htonl(*params); + params++; + *p++ = htonl(*val); + val++; } return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); @@ -4763,9 +4969,12 @@ int t4_alloc_mac_filt(struct adapter *ad int offset, ret = 0; struct fw_vi_mac_cmd c; unsigned int nfilters = 0; + unsigned int max_naddr = is_t4(adap) ? + NUM_MPS_CLS_SRAM_L_INSTANCES : + NUM_MPS_T5_CLS_SRAM_L_INSTANCES; unsigned int rem = naddr; - if (naddr > NUM_MPS_CLS_SRAM_L_INSTANCES) + if (naddr > max_naddr) return -EINVAL; for (offset = 0; offset < naddr ; /**/) { @@ -4806,10 +5015,10 @@ int t4_alloc_mac_filt(struct adapter *ad u16 index = G_FW_VI_MAC_CMD_IDX(ntohs(p->valid_to_idx)); if (idx) - idx[offset+i] = (index >= NUM_MPS_CLS_SRAM_L_INSTANCES + idx[offset+i] = (index >= max_naddr ? 0xffff : index); - if (index < NUM_MPS_CLS_SRAM_L_INSTANCES) + if (index < max_naddr) nfilters++; else if (hash) *hash |= (1ULL << hash_mac_addr(addr[offset+i])); @@ -4853,6 +5062,9 @@ int t4_change_mac(struct adapter *adap, int ret, mode; struct fw_vi_mac_cmd c; struct fw_vi_mac_exact *p = c.u.exact; + unsigned int max_mac_addr = is_t4(adap) ? + NUM_MPS_CLS_SRAM_L_INSTANCES : + NUM_MPS_T5_CLS_SRAM_L_INSTANCES; if (idx < 0) /* new allocation */ idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC; @@ -4867,10 +5079,10 @@ int t4_change_mac(struct adapter *adap, V_FW_VI_MAC_CMD_IDX(idx)); memcpy(p->macaddr, addr, sizeof(p->macaddr)); - ret = t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), &c); + ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); if (ret == 0) { ret = G_FW_VI_MAC_CMD_IDX(ntohs(p->valid_to_idx)); - if (ret >= NUM_MPS_CLS_SRAM_L_INSTANCES) + if (ret >= max_mac_addr) ret = -ENOMEM; *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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