Date: Thu, 17 Dec 1998 09:30:01 -0800 (PST) From: David Malone <dwmalone@maths.tcd.ie> To: freebsd-bugs@FreeBSD.ORG Subject: Re: kern/8928 450NX-based computers only probe the first PCI bus Message-ID: <199812171730.JAA29876@freefall.freebsd.org>
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The following reply was made to PR kern/8928; it has been noted by GNATS.
From: David Malone <dwmalone@maths.tcd.ie>
To: freebsd-gnats-submit@freebsd.org
Cc: Subject: Re: kern/8928 450NX-based computers only probe the first PCI bus
Date: Thu, 17 Dec 1998 17:20:14 +0000
I've been using the following patch on our Dell 6300 machine and it
seems to be working fine. If the number of busses is 255 I've just
set the number of busses to be NBUS - 2 if NBUS is defined or 10
otherwise. I had to include opt_smp.h to get NBUS...
David.
*** pcisupport.c.orig Wed Dec 2 22:29:31 1998
--- pcisupport.c Thu Dec 3 12:40:09 1998
***************
*** 42,47 ****
--- 42,48 ----
*/
#include "opt_pci.h"
+ #include "opt_smp.h"
#include <sys/param.h>
#include <sys/systm.h>
***************
*** 118,123 ****
--- 119,125 ----
* XXX Both fixbushigh_orion() and fixbushigh_i1225() are bogus in that way,
* that they store the highest bus number to scan in this device's config
* data, though it is about PCI buses attached to the CPU independently!
+ * The same goes for fixbushigh_450nx.
*/
static void
***************
*** 137,142 ****
--- 139,204 ----
tag->secondarybus = tag->subordinatebus = sublementarybus +1;
}
+
+ /*
+ * This reads the PCI config space for the 82451NX MIOC in the 450NX
+ * chipset to determine the PCI bus configuration.
+ *
+ * Assuming the BIOS has set up the MIOC properly, this will correctly
+ * report the number of PCI busses in the system.
+ *
+ * A small problem is that the Host to PCI bridge control is in the MIOC,
+ * while the host-pci bridges are separate PCI devices. So it really
+ * isn't easily possible to set up the subordinatebus mappings as the
+ * 82454NX PCI expander bridges are probed, although that makes the
+ * most sense.
+ */
+ static void
+ fixbushigh_450nx(pcici_t tag)
+ {
+ int subordinatebus;
+ unsigned long devmap;
+
+ /*
+ * Read the DEVMAP field, so we know which fields to check.
+ * If the Host-PCI bridge isn't marked as present by the BIOS,
+ * we have to assume it doesn't exist.
+ * If this doesn't find all the PCI busses, complain to the
+ * BIOS vendor. There is nothing more we can do.
+ */
+ devmap = pci_cfgread(tag, 0xd6, 2) & 0x3c;
+ if (!devmap)
+ panic("450NX MIOC: No host to PCI bridges marked present.\n");
+ /*
+ * Since the buses are configured in order, we just have to
+ * find the highest bus, and use those numbers.
+ */
+ if (devmap & 0x20) { /* B1 */
+ subordinatebus = pci_cfgread(tag, 0xd5, 1);
+ } else if (devmap & 0x10) { /* A1 */
+ subordinatebus = pci_cfgread(tag, 0xd4, 1);
+ } else if (devmap & 0x8) { /* B0 */
+ subordinatebus = pci_cfgread(tag, 0xd2, 1);
+ } else /* if (devmap & 0x4) */ { /* A0 */
+ subordinatebus = pci_cfgread(tag, 0xd1, 1);
+ }
+ if (subordinatebus == 255) {
+ printf("fixbushigh_450nx: bogus highest bus (%d) - reducing\n",
+ subordinatebus);
+ #ifdef NBUS
+ subordinatebus = NBUS - 2;
+ #else
+ subordinatebus = 10;
+ #endif
+ }
+ if (bootverbose)
+ printf("fixbushigh_450nx: subordinatebus is %d\n",
+ subordinatebus);
+
+ tag->secondarybus = tag->subordinatebus = subordinatebus;
+ }
+
+
static void
fixwsc_natoma(pcici_t tag)
{
***************
*** 231,236 ****
--- 293,299 ----
case 0x84c58086:
return ("Intel 82453KX/GX (Orion) PCI memory controller");
case 0x84ca8086:
+ fixbushigh_450nx(tag);
return ("Intel 82451NX Memory and I/O Controller");
case 0x84cb8086:
return ("Intel 82454NX PCI Expander Bridge");
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