Date: Sat, 19 Jul 1997 08:33:29 -0700 From: David Greenman <dg@root.com> To: Dennis <dennis@etinc.com> Cc: hackers@FreeBSD.ORG Subject: Re: fxpX: warning: unsupported PHY, type = 7, addr = 1 Message-ID: <199707191533.IAA20004@implode.root.com> In-Reply-To: Your message of "Sat, 19 Jul 1997 10:52:36 EDT." <3.0.32.19970719105230.00740168@etinc.com>
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>Any patch forthcoming for this message? Its a little embarrassing recommending
>a card and the first thing they get is a bunch of "unsupported" warning
>messages.
A fix was committed to 2.2-stable and -current more than a month ago.
-DG
David Greenman
Core-team/Principal Architect, The FreeBSD Project
Index: if_fxp.c
===================================================================
RCS file: /home/ncvs/src/sys/pci/if_fxp.c,v
retrieving revision 1.21.2.7
diff -c -r1.21.2.7 if_fxp.c
*** if_fxp.c 1997/04/23 01:49:12 1.21.2.7
--- if_fxp.c 1997/06/13 07:45:42
***************
*** 961,975 ****
csr->scb_command = FXP_SCB_COMMAND_RU_START;
/*
! * Toggle a few bits in the DP83840 PHY.
*/
! if (sc->phy_primary_device == FXP_PHY_DP83840 ||
! sc->phy_primary_device == FXP_PHY_DP83840A) {
fxp_mdi_write(sc->csr, sc->phy_primary_addr, FXP_DP83840_PCR,
fxp_mdi_read(sc->csr, sc->phy_primary_addr, FXP_DP83840_PCR) |
FXP_DP83840_PCR_LED4_MODE | /* LED4 always indicates duplex */
FXP_DP83840_PCR_F_CONNECT | /* force link disconnect bypass */
FXP_DP83840_PCR_BIT10); /* XXX I have no idea */
/*
* If link0 is set, disable auto-negotiation and then:
* If link1 is unset = 10Mbps
--- 961,978 ----
csr->scb_command = FXP_SCB_COMMAND_RU_START;
/*
! * Toggle a few bits in the PHY.
*/
! switch (sc->phy_primary_device) {
! case FXP_PHY_DP83840:
! case FXP_PHY_DP83840A:
fxp_mdi_write(sc->csr, sc->phy_primary_addr, FXP_DP83840_PCR,
fxp_mdi_read(sc->csr, sc->phy_primary_addr, FXP_DP83840_PCR) |
FXP_DP83840_PCR_LED4_MODE | /* LED4 always indicates duplex */
FXP_DP83840_PCR_F_CONNECT | /* force link disconnect bypass */
FXP_DP83840_PCR_BIT10); /* XXX I have no idea */
+ /* fall through */
+ case FXP_PHY_82555:
/*
* If link0 is set, disable auto-negotiation and then:
* If link1 is unset = 10Mbps
***************
*** 981,999 ****
int flags;
flags = (ifp->if_flags & IFF_LINK1) ?
! FXP_DP83840_BMCR_SPEED_100M : 0;
flags |= (ifp->if_flags & IFF_LINK2) ?
! FXP_DP83840_BMCR_FULLDUPLEX : 0;
! fxp_mdi_write(sc->csr, sc->phy_primary_addr, FXP_DP83840_BMCR,
! (fxp_mdi_read(sc->csr, sc->phy_primary_addr, FXP_DP83840_BMCR) &
! ~(FXP_DP83840_BMCR_AUTOEN | FXP_DP83840_BMCR_SPEED_100M |
! FXP_DP83840_BMCR_FULLDUPLEX)) | flags);
} else {
! fxp_mdi_write(sc->csr, sc->phy_primary_addr, FXP_DP83840_BMCR,
! (fxp_mdi_read(sc->csr, sc->phy_primary_addr, FXP_DP83840_BMCR) |
! FXP_DP83840_BMCR_AUTOEN));
}
! } else {
printf("fxp%d: warning: unsupported PHY, type = %d, addr = %d\n",
ifp->if_unit, sc->phy_primary_device, sc->phy_primary_addr);
}
--- 984,1003 ----
int flags;
flags = (ifp->if_flags & IFF_LINK1) ?
! FXP_PHY_BMCR_SPEED_100M : 0;
flags |= (ifp->if_flags & IFF_LINK2) ?
! FXP_PHY_BMCR_FULLDUPLEX : 0;
! fxp_mdi_write(sc->csr, sc->phy_primary_addr, FXP_PHY_BMCR,
! (fxp_mdi_read(sc->csr, sc->phy_primary_addr, FXP_PHY_BMCR) &
! ~(FXP_PHY_BMCR_AUTOEN | FXP_PHY_BMCR_SPEED_100M |
! FXP_PHY_BMCR_FULLDUPLEX)) | flags);
} else {
! fxp_mdi_write(sc->csr, sc->phy_primary_addr, FXP_PHY_BMCR,
! (fxp_mdi_read(sc->csr, sc->phy_primary_addr, FXP_PHY_BMCR) |
! FXP_PHY_BMCR_AUTOEN));
}
! break;
! default:
printf("fxp%d: warning: unsupported PHY, type = %d, addr = %d\n",
ifp->if_unit, sc->phy_primary_device, sc->phy_primary_addr);
}
Index: if_fxpreg.h
===================================================================
RCS file: /home/ncvs/src/sys/pci/if_fxpreg.h,v
retrieving revision 1.3.2.3
diff -c -r1.3.2.3 if_fxpreg.h
*** if_fxpreg.h 1997/03/21 08:01:52 1.3.2.3
--- if_fxpreg.h 1997/06/13 07:38:42
***************
*** 292,306 ****
#define FXP_PHY_DP83840 4
#define FXP_PHY_80C240 5
#define FXP_PHY_80C24 6
#define FXP_PHY_DP83840A 10
/*
! * DP84830 PHY, BMCR Basic Mode Control Register
*/
! #define FXP_DP83840_BMCR 0x0
! #define FXP_DP83840_BMCR_FULLDUPLEX 0x0100
! #define FXP_DP83840_BMCR_AUTOEN 0x1000
! #define FXP_DP83840_BMCR_SPEED_100M 0x2000
/*
* DP84830 PHY, PCS Configuration Register
--- 292,307 ----
#define FXP_PHY_DP83840 4
#define FXP_PHY_80C240 5
#define FXP_PHY_80C24 6
+ #define FXP_PHY_82555 7
#define FXP_PHY_DP83840A 10
/*
! * PHY BMCR Basic Mode Control Register
*/
! #define FXP_PHY_BMCR 0x0
! #define FXP_PHY_BMCR_FULLDUPLEX 0x0100
! #define FXP_PHY_BMCR_AUTOEN 0x1000
! #define FXP_PHY_BMCR_SPEED_100M 0x2000
/*
* DP84830 PHY, PCS Configuration Register
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