Date: Fri, 22 May 1998 09:57:15 +0930 From: Greg Lehey <grog@lemis.com> To: Jamie Bowden <jamie@itribe.net>, Peter Jeremy <peter.jeremy@alcatel.com.au> Cc: hackers@FreeBSD.ORG Subject: Re: Intel vs the rest (was `Original PC' and `talk') Message-ID: <19980522095715.R27201@freebie.lemis.com> In-Reply-To: <Pine.SGI.3.96.980521083324.1012M-100000@animaniacs.itribe.net>; from Jamie Bowden on Thu, May 21, 1998 at 08:36:38AM -0400 References: <199805202156.HAA15942@gsms01.alcatel.com.au> <Pine.SGI.3.96.980521083324.1012M-100000@animaniacs.itribe.net>
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On Thu, 21 May 1998 at 8:36:38 -0400, Jamie Bowden wrote:
> On Thu, 21 May 1998, Peter Jeremy wrote:
>
>> As an example of the impact of an architectural decision on
>> complexity: The 68k included a clear split between (non-modifiable)
>> instructions and (modifiable) data, the x86 didn't (and early
>> applications often used self-modifying code). This means that the x86
>> needs a unified cache, whilst the 68k uses a split cache - which gives
>> it two immediate advantages: The I-cache is also somewhat simpler (no
>> need for dirty bits or the write-{through,back} logic), allowing more
>> of it for the same complexity. Dual caches allow parallel I and D
>> accesses - ie effectively doubling the cache <-> CPU bandwidth (dual-
>> porting the cache can be done, but entails a substantial increase in
>> complexity). (The downside is that a unified cache will adjust to
>> different code vs data footprints - giving somewhat better hit rates
>> for a given total cache size).
>
> I have both.
>
> Data cache size: 16 Kbytes
> Instruction cache size: 16 Kbytes
> Secondary unified instruction/data cache size: 512 Kbytes on Processor 0
>
> All hail high end workstation makers. This is the SGI on my desk, lowly
> Indy that it is.
And how large is the TLB? And the page size?
Greg
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